Inventor

NANJUNDIAH BHAVANI SHRINGARI

IN4 patents

⚠️ This page may combine multiple inventors who share the name “NANJUNDIAH BHAVANI SHRINGARI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

3 patents

US7647539B2Jan 12, 2010

System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation

IBM29 citations91

US7584394B2Sep 1, 2009

System and method for pseudo-random test pattern memory allocation for processor design verification and validation

IBM7 citations72

US7689886B2Mar 30, 2010

System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation

IBM7 citations71

ARORA SAMPAN

1 patent

US8127192B2Feb 28, 2012

Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode

ARORA SAMPAN4 citations54