Inventor

GARDNER SANAZ K

US50 patents

⚠️ This page may combine multiple inventors who share the name “GARDNER SANAZ K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GARDNER SANAZ K

INTEL CORP

Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

Ge nano wire transistor with GaAs as the sacrificial layer

III-N epitaxial device structures on free standing silicon mesas

N-channel gallium nitride transistors

Nonplanar III-N transistors with compositionally graded semiconductor channels

Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack

Nonplanar III-N transistors with compositionally graded semiconductor channels

Techniques for monolithic co-integration of polycrystalline thin-film bulk acoustic resonator devices and monocrystalline III-N semiconductor transistor devices

Ge NANO wire transistor with GAAS as the sacrificial layer

Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

Nanowire transistors with embedded dielectric spacers

Semiconductor devices with raised doped crystalline structures

Integration of III-V devices on Si wafers

High electron mobility transistors with localized sub-fin isolation

Integrated circuit die having reduced defect group III-nitride layer and methods associated therewith

Methods and structures to prevent sidewall defects during selective epitaxy

Integration of III-V devices on Si wafers

Offstate parasitic leakage reduction for tunneling field effect transistors

Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof

III-N devices in Si trenches

Gallium nitride (GaN) transistor structures on a substrate

III-N epitaxial device structures on free standing silicon mesas

Gate stack design for GaN e-mode transistor performance

Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances

Semiconductor device with released source and drain

Gate stack design for GaN e-mode transistor performance

N-channel gallium nitride transistors

Transistors having ultra thin fin profiles and their methods of fabrication

Heteroepitaxial structures with high temperature stable substrate interface material

Ingaas epi structure and wet etch process for enabling III-v GAA in art trench

Group III-N MEMS structures on a group IV substrate

Method to achieve a uniform Group IV material layer in an aspect ratio trapping trench

III-V finfet transistor with V-groove S/D profile for improved access resistance

Envelope-tracking control techniques for highly-efficient RF power amplifiers

Multiple stacked field-plated GaN transistor and interlayer dielectrics to improve breakdown voltage and reduce parasitic capacitances

Self-aligned transistor structures enabling ultra-short channel lengths

Semiconductor devices with raised doped crystalline structures

Methods and structures to prevent sidewall defects during selective epitaxy

High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin

Method of fabricating semiconductor structures on dissimilar substrates

III-N devices in Si trenches

Transistors including retracted raised source/drain to reduce parasitic capacitances

Integrated circuit die having reduced defect group III-nitride structures and methods associated therewith

Method of fabricating semiconductor structures on dissimilar substrates

THEN HAN WUI

Nonplanar III-N transistors with compositionally graded semiconductor channels

Group III-N transistors on nanoscale template structures

TAHOE RES LTD

Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances

Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances

RADOSAVLJEVIC MARKO

Non-planar semiconductor device having channel region with low band-gap cladding layer

GOEL NITI

Epitaxial film growth on patterned substrate