Inventor

BISWAS SUKALPA

US73 patents

⚠️ This page may combine multiple inventors who share the name “BISWAS SUKALPA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BISWAS SUKALPA

APPLE INC

Memory arbitration techniques based on latency tolerance

Memory access quality-of-service reallocation

Combined single error correction/device kill detection code

Systems and methods for monitoring and controlling repetitive accesses to volatile memory

Memory system having combined high density, low bandwidth and low density, high bandwidth memories

Storing address of spare in failed memory location

Storing address of spare in failed memory location

Mechanism for sharing private caches in a SoC

System cache with partial write valid states

System cache with speculative read engine

System cache with fine grain power management

Write/read turn techniques based on latency tolerance

Calibration of clock signal for data transmission

System cache with sticky removal engine

Memory controller with loopback test interface

Memory access scheduling using category arbitration

Cache allocation scheme optimized for browsing applications

Memory power savings in idle display case

Oversampling-based scheme for synchronous interface communication

Memory system having combined high density, low bandwidth and low density, high bandwidth memories

Memory system having combined high density, low bandwidth and low density, high bandwidth memories

Memory system having combined high density, low bandwidth and low density, high bandwidth memories

Storing address of spare in failed memory location

QoS-aware scheduling

Dynamic QoS upgrading

Method and apparatus for optimizing calibrations of a memory subsystem

Ordering memory requests based on access efficiency

Advanced coarse-grained cache power management

Memory power savings in idle display case

Systems and methods for dynamically switching memory performance states

BISWAS SUKALPA

Memory controller with QoS-aware scheduling

Memory system having combined high density, low bandwidth and low density, high bandwidth memories

Matrix for numerical comparison

Dynamic QoS upgrading

Reordering in the memory controller

System cache with sticky allocation

System cache with cache hint control

Proportional memory operation throttling

Multiple critical word bypassing in a memory controller

Accelerating memory operations blocked by ordering requirements and data not yet received

OPTI INC

Method and apparatus for arbitrating requests at two or more levels of priority using a single request line

Refresh-ahead and burst refresh preemption technique for managing DRAM in computer system

Compact ISA-bus interface

Compact ISA-bus interface

Compact ISA-bus interface

SAUND GURJEET S

Bandwidth management

Quality of service (QoS)-related fabric control

BODROZIC LUKA

Memory controller with loopback test interface

Memory controller with loopback test interface

CHEN HAO

Dynamic data strobe detection