Inventor

TAJALLI ARMIN

US90 patents

⚠️ This page may combine multiple inventors who share the name “TAJALLI ARMIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAJALLI ARMIN

Kandou Labs SA

Methods and systems for providing multi-stage distributed decision feedback equalization

Voltage sampler driver with enhanced high-frequency gain

Lock detector for phase lock loop

Symmetric is linear equalization circuit with increased gain

Method and system for calibrating multi-wire skew

Phase rotation circuit for eye scope measurements

Multi-modal data-driven clock recovery circuit

Method for measuring and correcting multi-wire skew

Method for measuring and correcting multi-wire skew

Passive multi-input comparator for orthogonal codes on a multi-wire bus

Phase rotation circuit for eye scope measurements

Multi-modal data-driven clock recovery circuit

Synchronously-switched multi-input demodulating comparator

High performance phase locked loop

Clock data recovery in multilane data receiver

Vector signaling codes for densely-routed wire groups

Multi-stage sampler with increased gain

High performance phase locked loop

High speed communications system

Multi-modal data-driven clock recovery circuit

Data-driven phase detector element for phase locked loops

Method for measuring and correcting multi-wire skew

High performance phase locked loop

Matrix phase interpolator for phase locked loop

Voltage sampler driver with enhanced high-frequency gain

Programmable continuous time linear equalizer having stabilized high-frequency peaking for controlling operating current of a slicer

Quadrature and duty cycle error correction in matrix phase lock loop

Sampler with low input kickback

High speed communications system

Multi-stage sampler with increased gain

Method and system for calibrating multi-wire skew

Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation

Data-driven phase detector element for phase locked loops

Multiphase data receiver with distributed DFE

Quadrature and duty cycle error correction in matrix phase lock loop

Symmetric linear equalization circuit with increased gain

Enhanced phase interpolation circuit

Symmetric linear equalization circuit with increased gain

Efficient processing and detection of balanced codes

Low power multilevel driver for generating wire signals according to summations of a plurality of weighted analog signal components having wire-specific sub-channel weights

Dynamic integration time adjustment of a clocked data sampler using a static analog calibration circuit

Low power multilevel driver for generating wire signals according to summations of a plurality of weighted analog signal components having wire-specific sub-channel weights

Linear phase interpolation circuit

Phase interpolation circuit

Multiple adjacent slicewise layout of voltage-controlled oscillator

Multiple adjacent slicewise layout of voltage-controlled oscillator

Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation

CRONIE HARM

Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes

TAJALLI ARMIN

Efficient processing and detection of balanced codes

ECOLE POLYTECH

Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes