Inventor

WARKENTIN ANDREI

US72 patents

⚠️ This page may combine multiple inventors who share the name “WARKENTIN ANDREI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WARKENTIN ANDREI

VMWARE INC

Hypervisor context switching using a redirection exception vector in processors having more than two hierarchical privilege levels

Hypervisor context switching using TLB tags in processors having more than two hierarchical privilege levels

Memory management in virtualized computing systems having processors with more than two hierarchical privilege levels

Implementing upcall from secure to non-secure mode by injecting exception into non-secure mode

Partitioning a hypervisor into virtual hypervisors

Supporting PCI-e message-signaled interrupts in computer system with shared peripheral interrupts

Hardware-assisted guest address space scanning in a virtualized computing system

Providing fallback drivers for IO devices in a computing system

Virtual appliance supporting multiple instruction set architectures

Optimizing host CPU usage based on virtual machine guest OS power and performance management

Secondary CPU MMU initialization using page fault exception

Remote provisioning of hosts in public clouds

Remote provisioning of hosts in public clouds

Unifying hardware trusted execution environment technologies using virtual secure enclave device

System and method for providing secure execution environments using virtualization technology

Optimizing host CPU usage based on virtual machine guest OS power and performance management

System and method for implementing trusted execution environment on PCI device

Hypercall implementation in a virtualized computer system

Optimizing host CPU usage based on virtual machine guest OS power and performance management

Negative path testing in a bootloader environment

Remote provisioning of hosts in public clouds

Implementing interrupt remapping via input/output memory management unit faults

Supporting soft reboot in multi-processor systems without hardware or firmware control of processor state

Method for switching address spaces via an intermediate address space

Enabling efficient guest access to peripheral component interconnect express (PCIe) configuration space

Constructing bootloader address space without guaranteed physical memory layout

Unified hypervisor image for multiple processor ISAs

Trust domains for peripheral devices

Method for converting device tree data into ACPI data for edge device operating in a network

Non-unified cache coherency maintenance for virtual machines

Implementing firmware runtime services in a computer system

Implementing per-processor memory areas with non-preemptible operations using virtual aliases

Headless support using serial-based virtual consoles in a computing system

Virtualization detection in a computing system

Negative path testing in a bootloader environment

Implementing per-processor memory areas with non-preemptible operations using virtual aliases

Hypervisor backdoor interface

Hypervisor context switching using a trampoline scheme in processors having more than two hierarchical privilege levels

Safely discovering secure monitors and hypervisor implementations in systems operable at multiple hierarchical privilege levels

Exposing memory-mapped IO devices to drivers through firmware

Intelligent UEFI run-time services address space management

VMware LLC

Exposing PCIE configuration spaces as ECAM compatible

Enabling efficient guest access to peripheral component interconnect express (PCIe) configuration space

Device tree runtime mechanism

Lifecycle and recovery for virtualized DPU management operating systems

Power efficient memory value updates for arm architectures

MICROSOFT TECHNOLOGY LICENSING LLC

Intelligent boot device selection and recovery

Intelligent boot device selection and recovery

WARKENTIN ANDREI

Intelligent boot device selection and recovery

CLEETON LAWRENCE R

Virtual machine fast emulation assist