Inventor

DUCHESNE REGIS

CH26 patents

⚠️ This page may combine multiple inventors who share the name “DUCHESNE REGIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DUCHESNE REGIS

VMWARE INC

Hardware-assisted guest address space scanning in a virtualized computing system

Virtual appliance supporting multiple instruction set architectures

Optimizing host CPU usage based on virtual machine guest OS power and performance management

Unifying hardware trusted execution environment technologies using virtual secure enclave device

Optimizing host CPU usage based on virtual machine guest OS power and performance management

Hypercall implementation in a virtualized computer system

Optimizing host CPU usage based on virtual machine guest OS power and performance management

Implementing interrupt remapping via input/output memory management unit faults

Supporting soft reboot in multi-processor systems without hardware or firmware control of processor state

Method for switching address spaces via an intermediate address space

Enabling efficient guest access to peripheral component interconnect express (PCIe) configuration space

Constructing bootloader address space without guaranteed physical memory layout

Unified hypervisor image for multiple processor ISAs

Method for converting device tree data into ACPI data for edge device operating in a network

Non-unified cache coherency maintenance for virtual machines

Implementing firmware runtime services in a computer system

Headless support using serial-based virtual consoles in a computing system

Virtualization detection in a computing system

Unified hypercall interface across processors in virtualized computing systems

Scaling a host virtual counter and timer in a virtualized computer system

Guest time scaling for a virtual machine in a virtualized computer system

Behavioral implementation of a double fault stack in a computer system

VMware LLC

Enabling efficient guest access to peripheral component interconnect express (PCIe) configuration space

Device tree runtime mechanism

Lifecycle and recovery for virtualized DPU management operating systems

Power efficient memory value updates for arm architectures