Inventor
WOLPERT DAVID
US31 patents
Patents
31 patentsUS12057387B2Aug 6, 2024
Decoupling capacitor inside gate cut trench
IBM2 citations73
US7508250B1Mar 24, 2009
Testing for normal or reverse temperature related delay variations in integrated circuits
IBM7 citations73
US10699050B2Jun 30, 2020
Front-end-of-line shape merging cell placement and optimization
IBM2 citations72
US11308257B1Apr 19, 2022
Stacked via rivets in chip hotspots
IBM2 citations71
US10885260B1Jan 5, 2021
Fin-based fill cell optimization
IBM4 citations70
US10896283B1Jan 19, 2021
Noise-based optimization for integrated circuit design
IBM2 citations65
US12500144B2Dec 16, 2025
Backside self aligned skip via
IBM0 citations62
US12382621B2Aug 5, 2025
Decoupling capacitor inside gate cut trench
IBM0 citations62
US12266393B2Apr 1, 2025
Negative capacitance for ferroelectric capacitive memory cell
IBM0 citations62
US11916099B2Feb 27, 2024
Multilayer dielectric for metal-insulator-metal capacitor
IBM0 citations62
US12271674B2Apr 8, 2025
Generating a power delivery network based on the routing of signal wires within a circuit design
IBM0 citations61
US11906570B2Feb 20, 2024
Processor frequency improvement based on antenna optimization
IBM0 citations61
US11754615B2Sep 12, 2023
Processor frequency improvement based on antenna optimization
IBM0 citations61
US11822867B2Nov 21, 2023
Hierarchical color decomposition of process layers with shape and orientation requirements
IBM0 citations59
US11055465B2Jul 6, 2021
Fill techniques for avoiding Boolean DRC failures during cell placement
IBM0 citations59
US12381149B2Aug 5, 2025
Cell optimization through source resistance improvement
IBM0 citations56
US11663391B2May 30, 2023
Latch-up avoidance for sea-of-gates
IBM0 citations56
US11586798B1Feb 21, 2023
Avoiding electrostatic discharge events from cross-hierarchy tie nets
IBM1 citations56
US12575402B2Mar 10, 2026
Non-planar metal-insulator-metal structure
IBM0 citations52
US12362278B2Jul 15, 2025
Transistors with dual power and signal lines
IBM0 citations52
US10831980B2Nov 10, 2020
Using unused wires on very-large-scale integration chips for power supply decoupling
IBM0 citations51
US10586009B2Mar 10, 2020
Hierarchical trim management for self-aligned double patterning
IBM0 citations51
US10503864B1Dec 10, 2019
Using unused wires on very-large-scale integration chips for power supply decoupling
IBM0 citations51
US12176289B2Dec 24, 2024
Semiconductor device design mitigating latch-up
IBM0 citations50
US11830778B2Nov 28, 2023
Back-side wafer modification
IBM0 citations50
US11106850B2Aug 31, 2021
Flexible constraint-based logic cell placement
IBM0 citations50
US12112114B2Oct 8, 2024
Hierarchical color decomposition of library cells with boundary-aware color selection
IBM0 citations48
US11916384B2Feb 27, 2024
Region-based power grid generation through modification of an initial power grid based on timing analysis
IBM0 citations48
US11941340B2Mar 26, 2024
Cross-hierarchy antenna condition verification
IBM0 citations46
US12412020B2Sep 9, 2025
Effective metal density screens for hierarchical design rule checking (DRC) analysis
IBM0 citations45
US11487308B2Nov 1, 2022
Ensuring IoT device functionality in the presence of multiple temperature dependencies
IBM0 citations41