P

Inventor

RAMADOSS MURALI

US134 patents
⚠️ This page may combine multiple inventors who share the name “RAMADOSS MURALI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

45 patents
US11620256B2Apr 4, 2023

Systems and methods for improving cache efficiency and utilization

INTEL CORP36 citations97
US10043232B1Aug 7, 2018

Compute cluster preemption within a general-purpose graphics processing unit

INTEL CORP22 citations94
US10178619B1Jan 8, 2019

Advanced graphics power state management

INTEL CORP12 citations92
US9142001B2Sep 22, 2015

Performance allocation method and apparatus

INTEL CORP18 citations92
US6600493B1Jul 29, 2003

Allocating memory based on memory device organization

INTEL CORP26 citations91
US12210477B2Jan 28, 2025

Systems and methods for improving cache efficiency and utilization

INTEL CORP2 citations85
US11037269B1Jun 15, 2021

High-speed resume for GPU applications

INTEL CORP11 citations84
US10909039B2Feb 2, 2021

Data prefetching for graphics data processing

INTEL CORP5 citations84
US10482562B2Nov 19, 2019

Graphics engine partitioning mechanism

INTEL CORP8 citations84
US10109078B1Oct 23, 2018

Controlling coarse pixel size from a stencil buffer

INTEL CORP5 citations84
US7243041B2Jul 10, 2007

GUID, PnPID, isochronous bandwidth based mechanism for achieving memory controller thermal throttling

INTEL CORP10 citations84
US11016929B2May 25, 2021

Scalar core integration

INTEL CORP7 citations83
US10999797B2May 4, 2021

Advanced graphics power state management

INTEL CORP5 citations83
US10560892B2Feb 11, 2020

Advanced graphics power state management

INTEL CORP4 citations83
US8386808B2Feb 26, 2013

Adaptive power budget allocation between multiple components in a computing system

INTEL CORP7 citations80
US11869119B2Jan 9, 2024

Controlling coarse pixel size from a stencil buffer

INTEL CORP2 citations73
US11762804B2Sep 19, 2023

Scalar core integration

INTEL CORP1 citations73
US11409693B2Aug 9, 2022

Scalar core integration

INTEL CORP2 citations73
US11232536B2Jan 25, 2022

Thread prefetch mechanism

INTEL CORP2 citations73
US11062506B2Jul 13, 2021

Tile-based immediate mode rendering with early hierarchical-z

INTEL CORP3 citations73
US10930060B2Feb 23, 2021

Conditional shader for graphics

INTEL CORP2 citations73
US10706591B2Jul 7, 2020

Controlling coarse pixel size from a stencil buffer

INTEL CORP1 citations73
US10672175B2Jun 2, 2020

Order independent asynchronous compute and streaming for graphics

INTEL CORP2 citations73
US10643374B2May 5, 2020

Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer

INTEL CORP3 citations73
US10282812B2May 7, 2019

Page faulting and selective preemption

INTEL CORP2 citations73
US10191759B2Jan 29, 2019

Apparatus and method for scheduling graphics processing unit workloads from virtual machines

INTEL CORP5 citations73
US9396032B2Jul 19, 2016

Priority based context preemption

INTEL CORP5 citations73
US11127106B2Sep 21, 2021

Runtime flip stability characterization

INTEL CORP2 citations72
US10997086B1May 4, 2021

Systems and methods in a graphics environment for providing shared virtual memory addressing support for a host system

INTEL CORP3 citations72
US10261570B2Apr 16, 2019

Managing graphics power consumption and performance

INTEL CORP2 citations72
US10162405B2Dec 25, 2018

Graphics processor power management contexts and sequential control loops

INTEL CORP2 citations72
US11443406B2Sep 13, 2022

High-speed resume for GPU applications

INTEL CORP3 citations71
US11055809B2Jul 6, 2021

Apparatus and method for provisioning virtualized multi-tile graphics processing hardware

INTEL CORP3 citations71
US10937119B2Mar 2, 2021

Apparatus and method for virtualized scheduling of multiple duplicate graphics engines

INTEL CORP2 citations71
US10607392B2Mar 31, 2020

Scatter gather engine

INTEL CORP2 citations71
US10332302B2Jun 25, 2019

Scatter gather engine

INTEL CORP2 citations71
US10192281B2Jan 29, 2019

Graphics command parsing mechanism

INTEL CORP2 citations70
US10410311B2Sep 10, 2019

Method and apparatus for efficient submission of workload to a high performance graphics sub-system

INTEL CORP2 citations67
US12131402B2Oct 29, 2024

Page faulting and selective preemption

INTEL CORP0 citations63
US12067641B2Aug 20, 2024

Page faulting and selective preemption

INTEL CORP0 citations63
US11871142B2Jan 9, 2024

Synergistic temporal anti-aliasing and coarse pixel shading technology

INTEL CORP0 citations63
US11715174B2Aug 1, 2023

Compute cluster preemption within a general-purpose graphics processing unit

INTEL CORP0 citations63
US11663774B2May 30, 2023

Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method

INTEL CORP0 citations63
US11636567B2Apr 25, 2023

Mutli-frame renderer

INTEL CORP0 citations63
US11354769B2Jun 7, 2022

Page faulting and selective preemption

INTEL CORP0 citations63

SAMSON ERIC

1 patent

Koston Joseph

1 patent

VEAL BRYAN E

1 patent

KOKER ALTUG

1 patent

VEMBU BALAJI

1 patent

Showing the top 50 of 134 patents by PatentIndex Score.