P

Inventor

SHE YONG

CN24 patents
⚠️ This page may combine multiple inventors who share the name “SHE YONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

23 patents
US10910347B2Feb 2, 2021

Method, apparatus and system to interconnect packaged integrated circuit dies

INTEL CORP10 citations84
US9778688B2Oct 3, 2017

Flexible system-in-package solutions for wearable devices

INTEL CORP5 citations73
US11538746B2Dec 27, 2022

Vertical bond-wire stacked chip-scale package with application-specific integrated circuit die on stack, and methods of making same

INTEL CORP3 citations72
US11081451B2Aug 3, 2021

Die stack with reduced warpage

INTEL CORP2 citations72
US10991679B2Apr 27, 2021

Stair-stacked dice device in a system in package, and methods of making same

INTEL CORP2 citations72
US10930622B2Feb 23, 2021

Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same

INTEL CORP2 citations72
US10770434B2Sep 8, 2020

Stair-stacked dice device in a system in package, and methods of making same

INTEL CORP2 citations72
US10727208B2Jul 28, 2020

Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same

INTEL CORP2 citations72
US10396055B2Aug 27, 2019

Method, apparatus and system to interconnect packaged integrated circuit dies

INTEL CORP2 citations72
US10332899B2Jun 25, 2019

3D package having edge-aligned die stack with direct inter-die wire connections

INTEL CORP3 citations72
US9859255B1Jan 2, 2018

Electronic device package

INTEL CORP6 citations68
US12027496B2Jul 2, 2024

Film in substrate for releasing z stack-up constraint

INTEL CORP0 citations62
US11894344B2Feb 6, 2024

Power enhanced stacked chip scale package solution with integrated die attach film

INTEL CORP0 citations62
US11742284B2Aug 29, 2023

Interconnect structure fabricated using lithographic and deposition processes

INTEL CORP0 citations62
US11302671B2Apr 12, 2022

Power enhanced stacked chip scale package solution with integrated die attach film

INTEL CORP0 citations62
US10438916B2Oct 8, 2019

Wire bond connection with intermediate contact structure

INTEL CORP1 citations62
US11848281B2Dec 19, 2023

Die stack with reduced warpage

INTEL CORP0 citations61
US12046581B2Jul 23, 2024

Integrated circuit package with glass spacer

INTEL CORP0 citations60
US11393788B2Jul 19, 2022

Integrated circuit package with glass spacer

INTEL CORP0 citations60
US11990395B2May 21, 2024

Joint connection of corner non-critical to function (NCTF) ball for BGA solder joint reliability (SJR) enhancement

INTEL CORP0 citations58
US11830848B2Nov 28, 2023

Electronic device package

INTEL CORP0 citations51
US11881441B2Jan 23, 2024

Stacked die semiconductor package spacer die

INTEL CORP0 citations45
US10872832B2Dec 22, 2020

Pre-molded active IC of passive components to miniaturize system in package

INTEL CORP0 citations36

HUAWEI TECH CO LTD

1 patent