Inventor

OH REUM

KR33 patents

⚠️ This page may combine multiple inventors who share the name “OH REUM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OH REUM

SAMSUNG ELECTRONICS CO LTD

Latency control circuit and method thereof and an auto-precharge control circuit and method thereof

Memory device for performing internal process and operating method thereof

Memory systems, on-die termination (ODT) circuits, and method of ODT control

Memory device sampling data using control signal transmitted through TSV

Semiconductor memory device and method of operating a semiconductor device in a processor mode or a normal mode

Memory device for performing internal process and operating method thereof

Memory device for performing internal process and operating method thereof

High bandwidth memory device and system device having the same

Semiconductor apparatus, stack semiconductor apparatus, and test method of the stack semiconductor apparatus

Apparatus and method for determining on die termination modes in memory device

Input buffer circuit of a synchronous semiconductor memory device

Latency control circuit and method thereof and an auto-precharge control circuit and method thereof

Semiconductor device and semiconductor package including the semiconductor device

High bandwidth memory device and system device having the same

Wafer level methods of testing semiconductor devices using internally-generated test enable signals

Semiconductor device using a parallel bit operation and method of operating the same

Latency control circuit and method of latency control

Stacked memory device and a memory chip including the same

Stacked memory device and a memory chip including the same

High bandwidth memory device and system device having the same

High bandwidth memory device and system device having the same

Semiconductor device using different types of through-silicon-vias

Wafer level methods of testing semiconductor devices using internally-generated test enable signals

Wafer level methods of testing semiconductor devices using internally-generated test enable signals

Memory device comprising status circuit and operating method thereof

Method of operating memory device and memory device performing the same

Semiconductor die for determining load of through silicon via and semiconductor device including the same

Semiconductor die for determining load of through silicon via and semiconductor device including the same

Semiconductor memory device and system including the same

Semiconductor memory device and method of adjusting operation condition of the same

Stacked semiconductor device and system including the same

KIM MYEONG-O

Semiconductor memory device

PARK TAEK-SEON

Semiconductor memory device having reduced power consumption during latency