Inventor
ZHAO JOE W
US26 patents
⚠️ This page may combine multiple inventors who share the name “ZHAO JOE W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
20 patentsUS6204192B1Mar 20, 2001
Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures
LSI LOGIC CORP166 citations99
US6028015AFeb 22, 2000
Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption
LSI LOGIC CORP173 citations99
US6232658B1May 15, 2001
Process to prevent stress cracking of dielectric films on semiconductor wafers
LSI LOGIC CORP93 citations98
US5660682AAug 26, 1997
Plasma clean with hydrogen gas
LSI LOGIC CORP100 citations98
US5770520AJun 23, 1998
Method of making a barrier layer for via or contact opening of integrated circuit structure
LSI LOGIC CORP57 citations96
US5926720AJul 20, 1999
Consistent alignment mark profiles on semiconductor wafers using PVD shadowing
LSI LOGIC CORP64 citations94
US5994775ANov 30, 1999
Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same
LSI LOGIC CORP39 citations93
US5956613ASep 21, 1999
Method for improvement of TiN CVD film quality
LSI LOGIC CORP27 citations93
US6756674B1Jun 29, 2004
Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same
LSI LOGIC CORP36 citations92
US6368979B1Apr 9, 2002
Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
LSI LOGIC CORP52 citations92
US6297555B1Oct 2, 2001
Method to obtain a low resistivity and conformity chemical vapor deposition titanium film
LSI LOGIC CORP22 citations92
US6157087ADec 5, 2000
Consistent alignment mark profiles on semiconductor wafers using metal organic chemical vapor deposition titanium nitride protective layer
LSI LOGIC CORP22 citations92
US5895267AApr 20, 1999
Method to obtain a low resistivity and conformity chemical vapor deposition titanium film
LSI LOGIC CORP20 citations92
US6239499B1May 29, 2001
Consistent alignment mark profiles on semiconductor wafers using PVD shadowing
LSI LOGIC CORP18 citations91
US5789028AAug 4, 1998
Method for eliminating peeling at end of semiconductor substrate in metal organic chemical vapor deposition of titanium nitride
LSI LOGIC CORP17 citations84
US6059637AMay 9, 2000
Process for abrasive removal of copper from the back surface of a silicon substrate
LSI LOGIC CORP15 citations74
US6060787AMay 9, 2000
Consistent alignment mark profiles on semiconductor wafers using fine grain tungsten protective layer
LSI LOGIC CORP12 citations73
US5981352ANov 9, 1999
Consistent alignment mark profiles on semiconductor wafers using fine grain tungsten protective layer
LSI LOGIC CORP11 citations73
US5635244AJun 3, 1997
Method of forming a layer of material on a wafer
LSI LOGIC CORP16 citations72
US5953631ASep 14, 1999
Low stress, highly conformal CVD metal thin film
LSI LOGIC CORP1 citations52
CHEN CINTI X
3 patentsUS8402412B1Mar 19, 2013
Increasing circuit speed and reducing circuit leakage by utilizing a local surface temperature effect
CHEN CINTI X4 citations60
US8311659B1Nov 13, 2012
Identifying non-randomness in integrated circuit product yield
CHEN CINTI X2 citations60
US8166445B1Apr 24, 2012
Estimating Icc current temperature scaling factor of an integrated circuit
CHEN CINTI X2 citations59