Inventor
NAG SUDIP K
US29 patents
⚠️ This page may combine multiple inventors who share the name “NAG SUDIP K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
27 patentsUS6086631AJul 11, 2000
Post-placement residual overlap removal method for core-based PLD programming process
XILINX INC242 citations99
US6021423AFeb 1, 2000
Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations
XILINX INC159 citations99
US6789244B1Sep 7, 2004
Placement of clock objects under constraints
XILINX INC178 citations98
US7143380B1Nov 28, 2006
Method for application of network flow techniques under constraints
XILINX INC97 citations97
US6099583AAug 8, 2000
Core-based placement and annealing methods for programmable logic devices
XILINX INC68 citations96
US6766504B1Jul 20, 2004
Interconnect routing using logic levels
XILINX INC26 citations92
US6415425B1Jul 2, 2002
Method for analytical placement of cells using density surface representations
XILINX INC38 citations92
US7143378B1Nov 28, 2006
Method and apparatus for timing characterization of integrated circuit designs
XILINX INC11 citations84
US7051312B1May 23, 2006
Upper-bound calculation for placed circuit design performance
XILINX INC11 citations84
US6857115B1Feb 15, 2005
Placement of objects with partial shape restriction
XILINX INC15 citations84
US7072815B1Jul 4, 2006
Relocation of components for post-placement optimization
XILINX INC14 citations83
US6732349B1May 4, 2004
Method and apparatus for improving PIP coverage in programmable logic devices
XILINX INC18 citations83
US6289496B1Sep 11, 2001
Placement of input-output design objects into a programmable gate array supporting multiple voltage standards
XILINX INC17 citations82
US6507860B1Jan 14, 2003
System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs
XILINX INC6 citations74
US6317768B1Nov 13, 2001
System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs
XILINX INC4 citations74
US6167416ADec 26, 2000
System and method for RAM-partitioning to exploit parallelism of radix-2 elements in FPGAS
XILINX INC5 citations74
US7306977B1Dec 11, 2007
Method and apparatus for facilitating signal routing within a programmable logic device
XILINX INC7 citations73
US6484298B1Nov 19, 2002
Method and apparatus for automatic timing-driven implementation of a circuit design
XILINX INC11 citations73
US6983439B1Jan 3, 2006
Unified placer infrastructure
XILINX INC5 citations72
US6625795B1Sep 23, 2003
Method and apparatus for placement of input-output design objects into a programmable gate array
XILINX INC9 citations72
US6877040B1Apr 5, 2005
Method and apparatus for testing routability
XILINX INC9 citations71
US6711600B1Mar 23, 2004
System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs
XILINX INC3 citations63
US7725868B1May 25, 2010
Method and apparatus for facilitating signal routing within a programmable logic device
XILINX INC3 citations62
US7076758B1Jul 11, 2006
Using router feedback for placement improvements for logic design
XILINX INC6 citations62
US7240315B1Jul 3, 2007
Automated local clock placement for FPGA designs
XILINX INC4 citations59
US7398496B1Jul 8, 2008
Unified placer infrastructure
XILINX INC2 citations58
US9405871B1Aug 2, 2016
Determination of path delays in circuit designs
XILINX INC1 citations48