Inventor
KNIPS THOMAS J
US21 patents
Patents
21 patentsUS7064990B1Jun 20, 2006
Method and apparatus for implementing multiple column redundancy for memory
IBM29 citations92
US7437626B2Oct 14, 2008
Efficient method of test and soft repair of SRAM with redundancy
IBM21 citations91
US9136019B1Sep 15, 2015
Built-in testing of unused element on chip
IBM10 citations83
US7793173B2Sep 7, 2010
Efficient memory product for test and soft repair of SRAM with redundancy
IBM11 citations83
US7930601B2Apr 19, 2011
AC ABIST diagnostic method, apparatus and program product
IBM11 citations82
US7219275B2May 15, 2007
Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy
IBM7 citations72
US7076710B2Jul 11, 2006
Non-binary address generation for ABIST
IBM10 citations72
US7076706B2Jul 11, 2006
Method and apparatus for ABIST diagnostics
IBM10 citations70
US7009895B2Mar 7, 2006
Method for skip over redundancy decode with very low overhead
IBM5 citations63
US6584023B1Jun 24, 2003
System for implementing a column redundancy scheme for arrays with controls that span multiple data bits
IBM6 citations63
US9355746B2May 31, 2016
Built-in testing of unused element on chip
IBM2 citations62
US7073105B2Jul 4, 2006
ABIST address generation
IBM5 citations62
US7068554B1Jun 27, 2006
Apparatus and method for implementing multiple memory redundancy with delay tracking clock
IBM4 citations62
US11081202B2Aug 3, 2021
Failing address registers for built-in self tests
IBM1 citations61
US7529997B2May 5, 2009
Method for self-correcting cache using line delete, data logging, and fuse repair correction
IBM3 citations61
US7210084B2Apr 24, 2007
Integrated system logic and ABIST data compression for an SRAM directory
IBM4 citations58
US7380191B2May 27, 2008
ABIST data compression and serialization for memory built-in self test of SRAM with redundancy
IBM1 citations51
US7170320B2Jan 30, 2007
Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering
IBM1 citations51
US11657887B2May 23, 2023
Testing bit write operation to a memory array in integrated circuits
IBM0 citations50
US11069422B1Jul 20, 2021
Testing multi-port array in integrated circuits
IBM0 citations50
US9983261B2May 29, 2018
Partition-able storage of test results using inactive storage elements
IBM0 citations41