Inventor

NOVAKOVSKY LARISA

IL25 patents

⚠️ This page may combine multiple inventors who share the name “NOVAKOVSKY LARISA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NOVAKOVSKY LARISA

INTEL CORP

Masking a power state of a core of a processor

Method and apparatus for cache line write back operation

Apparatus and method to identify the source of an interrupt

Supporting hang detection and data recovery in microprocessor systems

Adaptive hierarchical cache policy in a microprocessor

Method and apparatus for error correction in a cache

Device, system and method of managing a resource request

Apparatus and method to identify the source of an interrupt

Apparatus and method to identify the source of an interrupt

Reduced power mode of a cache unit

Posting weakly ordered transactions

System, apparatus and method for probeless field scan of a processor

Adaptive hierarchical cache policy in a microprocessor

Device, system and method to facilitate disaster recovery for a multi-processor platform

Pipelined prefetcher for parallel advancement of multiple data streams

Systems and methods for enhancing BIOS performance by alleviating code-size limitations

Apparatus and method to transfer data packets between domains of a processor

Communicating via a mailbox interface of a processor

Core-only system management interrupt

Restricting clock signal delivery in a processor

NOVAKOVSKY LARISA

Cache circuit having a tag array with smaller latency than a data array

Multi latency configurable cache

SORANI IRIS

Cache memory staged reopen

RAIKIN SHLOMO

Apparatus and method for memory-hierarchy aware producer-consumer instruction

YIGZAW THEODROS

Apparatus and method for implement a multi-level memory hierarchy