Inventor

ZHU JIANGLI

US137 patents

⚠️ This page may combine multiple inventors who share the name “ZHU JIANGLI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHU JIANGLI

MICRON TECHNOLOGY INC

Enabling stripe-based operations for error recovery at a memory sub-system

Transferring data between clock domains using pulses across a queue

Write buffer management

Refreshing data stored at a memory component based on a memory component characteristic component

Open translation unit management using an adaptive read threshold

Internal management traffic regulation for memory sub-systems

Memory duty-cycle skew management

Write type indication command

Performing hybrid wear leveling operations based on a sub-total write counter

Scanning techniques for a media-management operation of a memory sub-system

Hardware based status collector acceleration engine for memory sub-system operations

Unmap data pattern for coarse mapping memory sub-system

Memory sub-system including an in-package sequencer to perform error correction and memory testing operations

Performing hybrid wear leveling operations based on a sub-total write counter

Buffer allocation for reducing block transit penalty

Multiple-pass programming of memory cells using temporary parity generation

Managing an adjustable write-to-read delay of a memory sub-system

Detect whether die or channel is defective to confirm temperature data

Managing host input/output in a memory system executing a table flush

Arbiter circuit for commands from multiple physical functions in a memory sub-system

Hybrid wear leveling for in-place data replacement media

Scheduling of read operations and write operations based on a data bus mode

Memory cell voltage level selection

Write determination counter

Selecting a write operation mode from multiple write operation modes

Apparatus with read level management and methods for operating the same

Decreasing a quantity of queues to adjust a read throughput level for a data recovery operation

Maintaining data consistency in a memory sub-system that uses hybrid wear leveling operations

Scheduling of read operations and write operations based on a data bus mode

Scanning techniques for a media-management operation of a memory sub-system

Write type indication command

Reset and replay of memory sub-system controller in a memory sub-system

Metadata-assisted encoding and decoding for a memory sub-system

Multi-level wear leveling for non-volatile memory

Performing hybrid wear leveling operations based on a sub-total write counter

Early decoding termination for a memory sub-system

Memory degradation detection and management

Operating memory device in performance mode

Management of write operations in a non-volatile memory device using a variable pre-read voltage level

Refreshing data stored at a memory component based on a memory component characteristic component

Write determination counter

VIA TECH INC

Non-volatile memory apparatus and address classification method thereof

Non-volatile memory device and control method thereof

Low-density parity-check apparatus and matrix trapping set breaking method

Non-volatile memory apparatus and on-the-fly self-adaptive read voltage adjustment method thereof

SANDISK ENTPR IP LLC

Universal and reconfigurable QC-LDPC encoder

Syndrome layered decoding for LDPC codes

Device and method for resolving an LM flag issue

JEON SEUNGJUNE

Adaptive LLR based on syndrome weight

CHEN XIAOHENG

Compressing data from multiple reads for error control management in memory systems