Inventor

SANO MICHIAKI

JP44 patents

⚠️ This page may combine multiple inventors who share the name “SANO MICHIAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SANO MICHIAKI

SANDISK TECHNOLOGIES LLC

Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings

Three-dimensional memory device containing drain select isolation structures and on-pitch channels and methods of making the same without an etch stop layer

Semiconductor device containing multilayer titanium nitride diffusion barrier and method of making thereof

Distortion-compensated wafer bonding method and apparatus using a temperature-controlled backside thermal expansion layer

Three-dimensional memory device having L-shaped word lines and a support structure and methods of making the same

Three-dimensional memory device having L-shaped word lines and methods of making the same

Three-dimensional memory device having select gate electrode that is thicker than word lines and method of making thereof

Multiheight contact via structures for a multilevel interconnect structure

Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same

Resistive RAM including air gaps between word lines and between vertical bit lines

Three-dimensional memory device containing word lines having vertical protrusion regions and methods of making the same

Bonded assembly containing side bonding structures and methods of manufacturing the same

Vertical field effect transistors including two-tier select gates and method of making the same

Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory

Three-dimensional memory device with composite charge storage structures and methods for forming the same

Three-dimensional devices with wedge-shaped contact region and method of making thereof

Three-dimensional memory device containing a replacement buried source line and methods of making the same

Methods and apparatus for three-dimensional nonvolatile memory

Three-dimensional memory device with punch-through-resistant word lines and methods for forming the same

Exposure focus leveling method using region-differentiated focus scan patterns

Three-dimensional memory device with locally modulated threshold voltages at drain select levels and methods of making the same

Spiral gas adsorption apparatus and method of using the same

Three-dimensional memory device including stairless word line contact structures and method of making the same

Three-dimensional memory device containing word line contacts which extend through drain-select-level isolation structures and methods of making the same

Semiconductor device having edge seal and method of making thereof without metal hard mask arcing

Three-dimensional memory device including stairless word line contact structures and method of making the same

Three dimensional memory device and method of making thereof by forming channel and memory film after word line replacement

Systems and methods for non-destructive inspection of semiconductor devices using reflective X-ray microscope tomographic imaging

Multiple vertical TFT structures for a vertical bit line architecture

SANDISK TECHNOLOGIES INC

Bottom recess process for an outer blocking dielectric layer inside a memory opening

Multiheight contact via structures for a multilevel interconnect structure

Set of stepped surfaces formation for a multilevel interconnect structure

Multiheight electrically conductive via contacts for a multilevel interconnect structure

Multiheight electrically conductive via contacts for a multilevel interconnect structure

Composite contact via structure containing an upper portion which fills a cavity within a lower portion

SANDISK 3D LLC

Concave word line and convex interlayer dielectric for protecting a read/write layer

Trench multilevel contact to a 3D memory array and method of making thereof

Concave word line and convex interlayer dielectric for protecting a read/write layer

Method for forming oxide below control gate in vertical channel thin film transistor

Methods of forming sidewall gates

TOKYO ELECTRON LTD

Plasma processing method

Etching method

TEXAS INSTRUMENTS INC

Semiconductor memory device and manufacturing method thereof

WESTERN DIGITAL TECH INC

Electrical overlay measurement methods and structures for wafer-to-wafer bonding