Inventor
KANAPATHIPILLAI RUBAN
US14 patents
Patents
14 patentsUS6842850B2Jan 11, 2005
DSP data type matching for operation using multiple functional units
INTEL CORP74 citations98
US7062637B2Jun 13, 2006
DSP operations with permutation of vector complex data type operands
INTEL CORP20 citations92
US6842845B2Jan 11, 2005
Methods and apparatuses for signal processing
INTEL CORP21 citations92
US6832306B1Dec 14, 2004
Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions
INTEL CORP41 citations92
US6598155B1Jul 22, 2003
Method and apparatus for loop buffering digital signal processing instructions
INTEL CORP37 citations92
US6557096B1Apr 29, 2003
Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types
INTEL CORP27 citations92
US6446195B1Sep 3, 2002
Dyadic operations instruction processor with configurable functional blocks
INTEL CORP25 citations92
US6643768B2Nov 4, 2003
Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder
INTEL CORP8 citations74
US6631461B2Oct 7, 2003
Dyadic DSP instructions for digital signal processors
INTEL CORP6 citations74
US6408376B1Jun 18, 2002
Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously
INTEL CORP10 citations74
US6988184B2Jan 17, 2006
Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations
INTEL CORP3 citations63
US6772319B2Aug 3, 2004
Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructions
INTEL CORP2 citations63
US6748516B2Jun 8, 2004
Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously
INTEL CORP3 citations63
US6766446B2Jul 20, 2004
Method and apparatus for loop buffering digital signal processing instructions
INTEL CORP5 citations62