Inventor

LIN YEONG-JYH

TW55 patents

⚠️ This page may combine multiple inventors who share the name “LIN YEONG-JYH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN YEONG-JYH

TAIWAN SEMICONDUCTOR MFG CO LTD

Structure and formation method of semiconductor device structure

3D trench capacitor for integrated passive devices

Method for alignment, process tool and method for wafer-level alignment

Methods for controlling warpage in packaging

Semiconductor wafer device and manufacturing method thereof

Mechanisms for forming bonding structures

Semiconductor device having a boundary structure, a package on package structure, and a method of making

Methods for controlling warpage in packaging

3D trench capacitor for integrated passive devices

Method for alignment, process tool and method for wafer-level alignment

Methods for controlling warpage in packaging

Semiconductor device having a boundary structure, a package on package structure, and a method of making

Methods for stud bump formation

Chip packages and methods of manufacture thereof

Packaging through pre-formed metal pins

Photolithography alignment process for bonded wafers

Deposition system for high accuracy patterning

Embedded backside memory on a field effect transistor

Embedded backside memory on a field effect transistor

Deposition system for high accuracy patterning

Wafer level transfer molding and apparatus for performing the same

Semiconductor structure and associated manufacturing method

Wafer-level underfill and over-molding

Semiconductor wafer device and manufacturing method thereof

Methods for forming apparatus for stud bump formation

Apparatus and method for wafer bonding

3D trench capacitor for integrated passive devices

Apparatus and method for wafer bonding

Mechanisms for forming bonding structures

Wafer-level underfill and over-molding

Methods for controlling warpage in packaging

Mechanical wafer alignment detection for bonding process

Mechanical wafer alignment detection for bonding process

Photolithography alignment process for bonded wafers

Photolithography alignment process for bonded wafers

Semiconductor device having a boundary structure, a package on package structure, and a method of making

Semiconductor wafer device and manufacturing method thereof

Packaging through pre-formed metal pins

Apparatus and method for wafer bonding

Stacked LED structure and associated manufacturing method

Wafer level transfer molding and apparatus for performing the same

Mechanisms for forming bonding structures

CHIPMOS TECHNOLOGIES INC

Zigzag-stacked package structure

COB type IC package to enhanced bondibility of bumps embedded in substrate and method for fabricating the same

TAIWAN SEMICONDUCTOR MFG

Methods for controlling warpage in packaging

CHIPMOS TECHNOLOGIES BERMUDA

High frequency IC package and method for fabricating the same

JANG BOR-PING

Wafer-level underfill and over-molding

LIN YEONG-JYH

Methods for stud bump formation and apparatus for performing the same

YU CHUN HUI

Method of forming interconnects for three dimensional integrated circuit

HWANG CHIEN LING

Apparatus for stud bump formation