Inventor

WUU JOHN J

US25 patents

⚠️ This page may combine multiple inventors who share the name “WUU JOHN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WUU JOHN J

ADVANCED MICRO DEVICES INC

Scheme for enabling die reuse in 3D stacked products

In memory logic functions using memory arrays

VSS bitcell sleep scheme involving modified bitcell for terminating sleep regions

Sidecar SRAM for high granularity in floor plan aspect ratio

Programmable write word line boost for low voltage memory operation

Pseudo-dynamic circuit for multi-voltage timing interlocks

Backside power delivery and power grid pattern to support 3D die stacking

Dual read port latch array bitcell

Split read port latch array bit cell

Dual-track bitline scheme for 6T SRAM cells

Folded cell layout for 6T SRAM cell

Latch bit cells

Write masked latch bit cell

Hybrid library latch array

Memory cell flipping for mitigating SRAM BTI

Memory including side-car arrays with irregular sized entries

Dynamic setup and hold times adjustment for memories

SRAM power savings and write assist

Method and apparatus for providing complimentary state retention

XILINX INC

ECC optimization

System and method for SEU detection and correction

Single event upset tolerant memory device

WUU JOHN J

Error detection device and methods thereof

HEWLETT PACKARD DEVELOPMENT CO

System and method for calibrating weak write test mode (WWTM)

GLOBALFOUNDRIES INC

Sensing device for floating body cell memory and method thereof