Inventor

CHHABRA AMIT

IN35 patents

⚠️ This page may combine multiple inventors who share the name “CHHABRA AMIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHHABRA AMIT

ADVANCED RISC MACH LTD

Bitcell architecture

Method of forming multi-stack transistors in a single semiconductor die

Sensor for performance variation of memory read and write characteristics

Transient sensing circuitry

Multi-bitcell structure with shared read port

Memory architecture

Multi-transistor stack architecture in a single vertical stack

Multi-transistor stack bitcell architecture

Sensor for performance variation of memory read and write characteristics

Ring oscillator based bitcell delay monitor

Voltage retention techniques

Fault detection circuitry

Self-timed memory with adaptive voltage scaling

ST MICROELECTRONICS INT NV

Multi-supply dual port register file

System and method for improving memory performance and identifying weak bits

System and method for automatic detection of power up for a dual-rail circuit

Body bias multiplexer for stress-free transmission of positive and negative supplies

System and method for automatic detection of power up for a dual-rail circuit

Ultra-low voltage temperature threshold detector

Apparatus and method for testing shadow logic

SYNAMEDIA LTD

Virtual set top

Systems and methods for detecting logos in a video stream

Virtual set top

Systems and methods for video content security

AMAZON TECH INC

Record-by-record live migration using segmentation

Segmentation of maintenance on distributed systems

Augmenting storage functionality using emulation of storage characteristics

Using emulation of storage characteristics to perform an access request translated between different protocols

POLLARD BANKNOTE LTD

Method and apparatus for dispensing funds in a lottery

Method of managing a lottery

Lottery with pre and post allocated results and post sale activation

ARM LTD

Multi-stack bitcell architecture

Circuit architecture in multi-dimensional monolithic structure

ST MICROELECTRONICS SA

Method of minimizing the operating voltage of an SRAM cell

ROY TANMOY

Method and apparatus for testing of a memory with redundancy elements