Inventor

XU ZHONGGUANG

US35 patents

⚠️ This page may combine multiple inventors who share the name “XU ZHONGGUANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

XU ZHONGGUANG

MICRON TECHNOLOGY INC

Adapting an error recovery process in a memory sub-system

Partial block handling in a non-volatile memory device

Open translation unit management using an adaptive read threshold

Managing a hybrid error recovery process in a memory sub-system

Performing select gate integrity checks to identify and invalidate defective blocks

Dynamic voltage setting optimization during lifetime of a memory device

Half good block handling with defective deck pre-programing in a memory sub-system

Power loss error detection using partial block handling

Partial block handling protocol in a non-volatile memory device

Selection of erase policy in a memory device

Managing an adaptive data path selection threshold for a memory sub-system

Performing select gate integrity checks to identify and invalidate defective blocks

Partial block handling in a non-volatile memory device

Adaptive frequency control for high-speed memory devices

Managing a hybrid error recovery process in a memory sub-system

Open translation unit management using an adaptive read threshold

Partial block handling protocol in a non-volatile memory device

Adapting an error recovery process in a memory sub-system

Adjusting read-level thresholds based on write-to-write delay

Managing execution of a scrub operation in view of an operating characteristic of a memory subsystem

Performing refresh operations of a memory device according to a dynamic refresh frequency

Temperature and inter-pulse delay factors for media management operations at a memory device

Adaptive frequency control for high-speed memory devices

Reliability health prediction by high-stress seasoning of memory devices

Managing execution of scrub operations in a memory sub-system

Optimizing data reliability using erase retention

Adaptive scans of memory devices of a memory sub-system

Select gate maintenance with adaptive scan frequency in a memory sub-system

Generating virtual blocks using partial good blocks

Selective data pattern write scrub for a memory system

Dynamic read-level thresholds in memory systems

Life time extension of memory device based on rating of individual memory units

Adaptive generation of memory partitions

Adaptive memory partition closure time

SANDISK TECHNOLOGIES LLC

Programming selection devices in non-volatile memory strings