Inventor

Lang Murong

US85 patents

⚠️ This page may combine multiple inventors who share the name “Lang Murong”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

Lang Murong

MICRON TECHNOLOGY INC

Optimized seasoning trim values based on form factors in memory sub-system manufacturing

Adjustment of read and write voltages using a space between threshold voltage distributions

Adapting an error recovery process in a memory sub-system

Managing threshold voltage drift based on a temperature-dependent slope of the threshold voltage drift of a memory sub-system

Partial block handling in a non-volatile memory device

Adaptive scanning of memory devices with supervised learning

Adaptive time sense parameters and overdrive voltage parameters for wordlines at corner temperatures in a memory sub-system

Adaptive sensing time for memory operations

Error avoidance for partially programmed blocks of a memory device

Open translation unit management using an adaptive read threshold

Managing a hybrid error recovery process in a memory sub-system

Performing select gate integrity checks to identify and invalidate defective blocks

Dynamic voltage setting optimization during lifetime of a memory device

Managing threshold voltage drift based on operating characteristics of a memory sub-system

Managing an adjustable write-to-read delay of a memory sub-system

Dynamic read calibration

Adaptive time sense parameters and overdrive voltage parameters for respective groups of wordlines in a memory sub-system

Adaptive time sense parameters and overdrive voltage parameters for wordlines at corner temperatures in a memory sub-system

Adaptive sensing time for memory operations

Managing threshold voltage drift based on operating characteristics of a memory sub-system

Memory cell voltage level selection

Adaptive time sense parameters and overdrive voltage parameters for respective groups of wordlines in a memory sub-system

Apparatus with read level management and methods for operating the same

Adjusting read voltage levels based on a temperature-dependent slope of the threshold voltage drift of a memory sub-system

Adjustment of read and write voltages using a space between threshold voltage distributions

Adaptive scanning of memory devices with supervised learning

Block family management for a virtual block

Power loss error detection using partial block handling

Error avoidance for partially programmed blocks of a memory device

Partial block handling protocol in a non-volatile memory device

Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices

Empty page scan operations adjustment

Managing an adaptive data path selection threshold for a memory sub-system

Performing select gate integrity checks to identify and invalidate defective blocks

Partial block handling in a non-volatile memory device

Adaptive enhanced corrective read based on write and read temperature

Adaptive frequency control for high-speed memory devices

Managing a hybrid error recovery process in a memory sub-system

Read window management in a memory system

Open translation unit management using an adaptive read threshold

Adaptive error avoidance in the memory devices

Padding in flash memory blocks

Read disturb management

Partial block handling protocol in a non-volatile memory device

Refresh of neighboring memory cells based on read status

Scaling factors for media management operations at a memory device

Empty page scan operations adjustment

SANDISK TECHNOLOGIES LLC

Manage source line bias to account for non-uniform resistance of memory cell source lines

Manage source line bias to account for non-uniform resistance of memory cell source lines

SANDISK TECHNOLOGIES INC

Adaptive determination of program parameter using program of erase rate