Inventor

YANG KUO-NAN

TW122 patents

⚠️ This page may combine multiple inventors who share the name “YANG KUO-NAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YANG KUO-NAN

TAIWAN SEMICONDUCTOR MFG CO LTD

System and method for back side signal routing

Power grid structures and method of forming the same

Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

Integrated circuit design method, system and computer program product

Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same

Semiconductor device including PG-aligned cells and method of generating layout of same

Logic cell structure and integrated circuit with the logic cell structure

Method for evaluating failure-in-time

FinFET with an asymmetric source/drain structure and method of making same

Power grid of integrated circuit

Power gating for three dimensional integrated circuits (3DIC)

Power rail for preventing DC electromigration

Semiconductor arrangement and method of making

System and computer program product for integrated circuit design

Integrated circuit and method of forming the same

Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

Circuit layouts and related methods

Semiconductor device including PG-aligned cells and method of generating layout of same

Integrated circuit and method of forming the same

Power grid, IC and method for placing power grid

Method and system of forming semiconductor device

Method of forming conductive grid of integrated circuit

Techniques based on electromigration characteristics of cell interconnect

Power gating for three dimensional integrated circuits (3DIC)

Power rail for preventing DC electromigration

Routing structure and method of forming the same

Metal lines for preventing AC electromigration

Integrated circuit and method of generating integrated circuit layout

Inter-cell leakage-reducing method of generating layout diagram and system for same

Semiconductor structure with contact rail and method for forming the same

TAIWAN SEMICONDUCTOR MFG

High performance PD SOI tunneling-biased MOSFET

Bonded SOI wafer with &lt;100&gt; device layer and &lt;110&gt; substrate for performance improvement

Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance

Method of fabricating a necked FINFET device

Method for fabricating a body contact in a Finfet structure and a device including the same

Power gating for three dimensional integrated circuits (3DIC)

FinFET with an asymmetric source/drain structure and method of making same

Cell and macro placement on fin grid

Channel doping extension beyond cell boundaries

Integrated circuit with standard cells

Method for fabricating a body contact in a finfet structure and a device including the same

System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE)

Contact structure of non-planar semiconductor device

YANG KUO NAN

EVA insole manufacturing process

EVA insole manufacturing process

EVA insole manufacturing process

EVA sole molding die assembly

(unassigned)

Method for forming air chamber in shoe sole

AIWA CO

Multiple-gap magnetic thin-film head with improved read/write coil arrangement

AMPEX

Method and apparatus for automatically adjusting the overshoot of a record head in response to the record head gap depth

Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement