Inventor

TOYAMA FUMIAKI

US66 patents

⚠️ This page may combine multiple inventors who share the name “TOYAMA FUMIAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TOYAMA FUMIAKI

SANDISK TECHNOLOGIES LLC

Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof

Through-memory-level via structures for a three-dimensional memory device

Three-dimensional memory device containing separately formed drain select transistors and method of making thereof

Through-memory-level via structures for a three-dimensional memory device

Through-memory-level via structures for a three-dimensional memory device

Multi-tier three-dimensional memory device containing dielectric well structures for contact via structures and methods of forming the same

Three-dimensional memory device including signal and power connection lines extending through dielectric regions and methods of making the same

Metal contact via structure surrounded by an air gap and method of making thereof

Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

Three-dimensional memory device having non-uniform spacing among memory stack structures and method of making thereof

Architecture for CMOS under array

Bonded assembly of semiconductor dies containing pad level across-die metal wiring and method of forming the same

Three-dimensional memory device including signal and power connection lines extending through dielectric regions and methods of making the same

Through-array conductive via structures for a three-dimensional memory device and methods of making the same

Non-volatile memory with multiple wells for word line switch transistors

Three-dimensional memory device containing horizontal and vertical word line interconnections and methods of forming the same

Three-dimensional memory device containing width-modulated connection strips and methods of forming the same

Bonded assembly with vertical power and control signal connection adjacent to sense amplifier regions and methods of forming the same

Three-dimensional memory device including contact-level bit-line-connection structures and methods of making the same

Memory die having wafer warpage reduction through stress balancing employing rotated three-dimensional memory arrays and method of making the same

Three dimensional memory device having well contact pillar and method of making thereof

Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof

Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same

Three-dimensional memory device with separated contact regions and methods for forming the same

Bonded assembly of a memory die and a logic die including laterally shifted bit-line bonding pads and methods of forming the same

Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof

Three-dimensional memory device containing dummy antenna diodes

Non-volatile memory with efficient signal routing

Capacitor structure including bonding pads as electrodes and methods of forming the same

Non-volatile memory with different use of metal lines in word line hook up regions

Three-dimensional memory device containing multiple size drain contact via structures and method of making same

Word line decoder circuitry under a three-dimensional memory array

Non-volatile memory with efficient word line hook-up

Non-volatile memory with different word line hook up regions based on pass through signals

SANDISK TECHNOLOGIES INC

Word line decoder circuitry under a three-dimensional memory array

Three dimensional memory device having well contact pillar and method of making thereof

Vertical NAND device with shared word line steps

Field effect transistor with a multilevel gate electrode for integration with a multilevel memory device

Field effect transistor with elevated active regions and methods of manufacturing the same

System to reduce stress on word line select transistor during erase operation

Wide and narrow patterning using common process

Non-volatile storage systems and methods

Methods for reducing body effect and increasing junction breakdown voltage

Non-volatile memory including bit line switch transistors formed in a triple-well

Bit line resistance compensation

Apparatus and methods for bonding pad redistribution layers in integrated circuits

SPANSION LLC

Mirror bit memory device applying a gate voltage alternately to gate

Semiconductor device and method for manufacturing

TOYAMA FUMIAKI

Back-biasing word line switch transistors

WESTERN DIGITAL TECH INC

Non-volatile memory with three dimensional stacked word line switches