Inventor
MITO MASAZI
JP2 patents
Patents
2 patentsUS4495693AJan 29, 1985
Method of integrating MOS devices of double and single gate structure
TOKYO SHIBAURA ELECTRIC CO71 citations92
US4453174AJun 5, 1984
Semiconductor integrated circuit device with non-volatile semiconductor memory cells and means for relieving stress therein
TOKYO SHIBAURA ELECTRIC CO9 citations72