Inventor

CHANG HUN-HSIEN

TW17 patents

⚠️ This page may combine multiple inventors who share the name “CHANG HUN-HSIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG HUN-HSIEN

TAIWAN SEMICONDUCTOR MFG

ESD protection circuit without overstress gate-driven effect

ESD bus lines in CMOS IC&#39;s for whole-chip ESD protection

SCR devices with deep-N-well structure for on-chip ESD protection circuits

Substrate-triggered technique for on-chip ESD protection circuit

Whole-chip ESD protection for CMOS ICs using bi-directional SCRs

Cascode LVTSCR and ESD protection circuit

Low-leakage diode string for use in the power-rail ESD clamp circuits

ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations

ESD protection scheme for mixed-voltage CMOS integrated circuits

Gate-coupled ESD protection circuit without transient leakage

CDM ESD protection design using deep N-well structure

ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications

ESD protection networks with NMOS-bound or PMOS-bound diode structures in a shallow-trench-isolation (STI) CMOS process

VDDCORE to VSS ESD clamp made of core device

Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regions

IND TECH RES INST

CMOS output buffer with CMOS-controlled lateral SCR devices

UNITED MICROELECTRONICS CORP

Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits

ESD bus lines in CMOS IC's for whole-chip ESD protection