Inventor

NGO HUNG C

US52 patents

⚠️ This page may combine multiple inventors who share the name “NGO HUNG C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NGO HUNG C

IBM

Dynamically scalable low voltage clock generation system

Dynamic leakage control circuit

Low gate-leakage virtual rail circuit

Power-gating cell for virtual power rail control

Control circuitry for power gating virtual power supply rails at differing voltage potentials

Multi-mode VCO

Limited switch dynamic logic circuit

Method and apparatus for performing rotate operations using cascaded multiplexers

Glitch-less clock selector

Clock divider with bypass and stop clock

Single register arbiter circuit

Scannable dynamic logic latch circuit

Cascaded pass-gate test circuit with interposed split-output drive devices

Dual-gate dynamic logic circuit with pre-charge keeper

Method and apparatus for fail-safe and restartable system clock generation

Controlled load limited switch dynamic logic circuitry

Interface circuit for coupling between logic circuit domains

Interleaved VCO with body voltage frequency range control

Voltage controlled oscillator with selectable frequency ranges

Limited switch dynamic logic circuit with keeper

Phase clock selector for generating a non-integer frequency division

Feedforward limited switch dynamic logic circuit

Duo-mode keeper circuit

Dual mode charge pump

Method and apparatus for performing add and rotate as a single instruction within a processor

Low power high frequency phase detector

Buffer/driver circuits

Limited switch dynamic logic selector circuits

Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance

Programmable local clock buffer

Parallel calculation of exponent and sticky bit during normalization

Circuit timing monitor having a selectable-path ring oscillator

Dynamic power and clock-gating method and circuitry with sleep mode based on estimated time for receipt of next wake-up signal

Circuit for controlling leakage

Adaptive phase locked loop

Low switching power limited switch dynamic logic

Pulsed local clock buffer (LCB) characterization ring oscillator

4-to-2 carry save adder using limited switching dynamic logic

Digital frequency multiplier circuit

Cascaded pass-gate test circuit with interposed split-output drive devices

Computing carry-in bit to most significant bit carry save adder in current stage

High performance, low power, dynamically latched up/down counter

CHANG LELAND

Test structure for characterizing multi-port static random access memory and register file arrays

Test structure for characterizing multi-port static random access memory and register file arrays

FLEISCHER BRUCE M

Automated critical area allocation in a physical synthesized hierarchical design

Method and system for a wiring-efficient permute unit

CHUANG CHING-TE K

Structure for high density stable static random access memory

High density stable static random access memory

INTERNATIIONAL BUSINESS MACHIN

Self limiting gate leakage driver

CHEN LEI

System and method for implementing simplified arithmetic logic unit processing of value-based control dependence sequences