Inventor

NEMAWARKAR SHASHANK

US32 patents

⚠️ This page may combine multiple inventors who share the name “NEMAWARKAR SHASHANK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NEMAWARKAR SHASHANK

SEAGATE TECHNOLOGY LLC

Method and apparatus to abort a command

Method and apparatus to delete a command queue

Method and apparatus to perform a function level reset in a memory controller

Method and apparatus to perform a function level reset in a memory controller

Volatile cache reconstruction after power failure

Method and apparatus to abort a command

Associative and atomic write-back caching system and method for storage subsystem

Cache offload based on predictive power parameter

Lockless parity management in a distributed data storage system

SUNDARARAMAN BALAKRISHNAN

Scheduling hierarchy in a traffic manager of a network processor

Modularized scheduling engine for traffic management in a network processor

Dynamic updating of scheduling hierarchy in a traffic manager of a network processor

Local messaging in a scheduling hierarchy in a traffic manager of a network processor

Packet draining from a scheduling hierarchy in a traffic manager of a network processor

Packet draining from a scheduling hierarchy in a traffic manager of a network processor

Shared task parameters in a scheduler of a network processor

NEWISYS INC

Synchronized communication between multi-processor clusters of multi-cluster computer systems

Communication between and within multi-processor clusters of multi-cluster computer systems

Reliable communication between multi-processor clusters of multi-cluster computer systems

Communication between multi-processor clusters of multi-cluster computer systems

Bandwidth, framing and error detection in communications between multi-processor clusters of multi-cluster computer systems

GLOBALFOUNDRIES US INC

Multi-port register file for partial-sum accumulation

Bias voltage generation circuit for memory devices

Apparatus and method for providing high throughput memory responses

IBM

Multithreaded processor efficiency by pre-fetching instructions for a scheduled thread

Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache

NEMAWARKAR SHASHANK

Multithreaded, superscalar scheduling in a traffic manager of a network processor

Hybrid address mutex mechanism for memory accesses in a network processor

AULAKH SHAILENDRA

Speculative task reading in a traffic manager of a network processor

SAMSUNG ELECTRONICS CO LTD

Method and apparatus to control the use of hierarchical branch predictors based on the effectiveness of their results

SONNIER DAVID

Root scheduling algorithm in a network processor

CONDOR COMPUTING CORP

Apparatus and method for selecting dynamic latency for level 2 cache