P

Inventor

MANOVIT CHAIYASIT

TH8 patents
⚠️ This page may combine multiple inventors who share the name “MANOVIT CHAIYASIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MANOVIT CHAIYASIT

4 patents
US8099703B1Jan 17, 2012

Method and system for verifying power-optimized electronic designs using equivalency checking

MANOVIT CHAIYASIT14 citations82
US8219946B1Jul 10, 2012

Method for clock gating circuits

MANOVIT CHAIYASIT11 citations80
US8423935B1Apr 16, 2013

Method and apparatus for verifying output-based clock gating

MANOVIT CHAIYASIT4 citations58
US8898401B2Nov 25, 2014

Methods and apparatuses for improving speculation success in processors

MANOVIT CHAIYASIT1 citations45

ORACLE AMERICA INC

2 patents
US7814378B2Oct 12, 2010

Verification of memory consistency and transactional memory

ORACLE AMERICA INC73 citations94
US7779393B1Aug 17, 2010

System and method for efficient verification of memory consistency model compliance

ORACLE AMERICA INC20 citations82

SUN MICROSYSTEMS INC

1 patent
US6892286B2May 10, 2005

Shared memory multiprocessor memory model verification system and method

SUN MICROSYSTEMS INC113 citations92

XILINX INC

1 patent
US7746116B1Jun 29, 2010

Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis

XILINX INC5 citations58