Inventor
POURMOUSAVIAN SEYEDNASER
IE8 patents
Patents
8 patentsUS10326454B2Jun 18, 2019
All-digital phase locked loop using switched capacitor voltage doubler
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US10171089B2Jan 1, 2019
PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications
TAIWAN SEMICONDUCTOR MFG CO LTD5 citations73
US12563823B2Feb 24, 2026
Device with a high efficiency voltage multiplier
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11764211B2Sep 19, 2023
Device with a high efficiency voltage multiplier
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11177810B2Nov 16, 2021
All-digital phase locked loop using switched capacitor voltage doubler
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US10862486B2Dec 8, 2020
All-digital phase locked loop using switched capacitor voltage doubler
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10756083B2Aug 25, 2020
Device with a high efficiency voltage multiplier
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51
US10277117B2Apr 30, 2019
Device with a voltage multiplier
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations41