Inventor

KOSA YASUNOBU

JP27 patents

⚠️ This page may combine multiple inventors who share the name “KOSA YASUNOBU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOSA YASUNOBU

HITACHI LTD

Forming memory transistors with varying gate oxide thicknesses

Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS

Semiconductor memory device with peripheral circuits

Method of manufacturing a semiconductor integrated circuit device

Semiconductor memory device

Method for manufacturing complementary insulated gate field effect transistors

Method for fabrication of n-channel MIS device

Semiconductor memory device and a method of manufacturing the same

Method of manufacturing semiconductor memory device

Semiconductor integrated circuit device and method of manufacturing the same

Method of fabricating a mis-type device by using a gate electrode and selectively implanted nitride layer

MOSFET antiparasitic layer

Interconnection structure for semiconductor integrated circuits

Multi-emitter transistor having heavily doped N+ regions surrounding base region of transistors

Semiconductor device having insulator film with different prescribed thickness portions

MOTOROLA INC

Dram with a vertical capacitor and transistor

Semiconductor device having a static-random-access memory cell

Vertical field-effect transistor and a semiconductor memory cell having the transistor

Methods of forming a vertical field-effect transistor and a semiconductor memory cell

Structure for shielding conductors

Process for forming a structure which electrically shields conductors

Field effect transistor having control and current electrodes positioned at a planar elevated surface and method of formation

Method for forming a lightly-doped drain (LDD) structure in a semiconductor device

Method for forming a buried contact

Process for forming a static-random-access memory cell

Field effect transistor having control and current electrodes positioned at a planar elevated surface

Static RAM cell with soft error immunity