Inventor

HAMILTON DARLENE G

US33 patents

⚠️ This page may combine multiple inventors who share the name “HAMILTON DARLENE G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAMILTON DARLENE G

ADVANCED MICRO DEVICES INC

Higher program VT and faster programming rates based on improved erase methods

Erase method for dual bit virtual ground flash

Soft program and soft program verify of the core cells in flash memory array

Tailored erase method using higher program VT and higher negative gate erase

Address sequencer within BIST (Built-in-Self-Test) system

Method of improving dynamic reference tracking for flash memory unit

On-chip repair of defective address of core flash memory cells

Negative gate erase

Charge injection

Data retention characteristics as a result of high temperature bake

Method and system for embedded chip erase verification

Single bit array edges

Higher program VT and faster programming rates based on improved erase methods

Memory device and method using positive gate stress to recover overerased cell

Method of protecting a memory array from charge damage during fabrication

Method of controlling program threshold voltage distribution of a dual cell memory device

Method of dual cell memory device operation for improved end-of-life read margin

Method of programming a dual cell memory device

System and method for multi-bit flash reads using dual dynamic references

Substrate bias for programming non-volatile memory

Pre-charge method for reading a non-volatile memory cell

Erase method for a dual bit memory cell

Method of programming dual cell memory device to store multiple data states per cell

Method of determining charge loss activation energy of a memory array

Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array

Method for fabricating nitride memory cells using a floating gate fabrication process

Elimination of n+ contact implant from flash technologies by replacement with standard double-diffused and n+ implants

SPANSION LLC

System and method for multi-bit flash reads using dual dynamic references

Multi-phase wordline erasing for flash memory

Multi-level operation in dual element cells using a supplemental programming level

FASL LLC

Dummy wordline for erase and bitline leakage

Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference

HAMILTON DARLENE G

Extending flash memory data retension via rewrite refresh