Inventor
CHO SUNG-SOO
US22 patents
⚠️ This page may combine multiple inventors who share the name “CHO SUNG-SOO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS6571333B1May 27, 2003
Initializing a memory controller by executing software in second memory to wakeup a system
INTEL CORP67 citations95
US5729762AMar 17, 1998
Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent
INTEL CORP55 citations95
US5862387AJan 19, 1999
Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller
INTEL CORP83 citations94
US5798951AAug 25, 1998
Method and apparatus for automatic un-preconditioned insertion/removal capability between a notebook computer and a docking station
INTEL CORP76 citations94
US6161157ADec 12, 2000
Docking system
INTEL CORP60 citations93
US5889964AMar 30, 1999
Method and apparatus for docking and undocking a notebook computer to and from a docking station while the notebook computer is in an active state
INTEL CORP70 citations93
US5664197ASep 2, 1997
Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller
INTEL CORP71 citations93
US6782472B2Aug 24, 2004
Method of initializing a memory controller by executing software in a second memory to wake up a system
INTEL CORP25 citations92
US6442697B1Aug 27, 2002
Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems
INTEL CORP28 citations92
US5862389AJan 19, 1999
Method and apparatus for selectively invoking a particular interrupt service routine for a particular interrupt request
INTEL CORP29 citations92
US5465367ANov 7, 1995
Slow memory refresh in a computer with a limited supply of power
INTEL CORP88 citations92
US6055372AApr 25, 2000
Serial interrupt bus protocol
INTEL CORP19 citations91
US5983354ANov 9, 1999
Method and apparatus for indication when a bus master is communicating with memory
INTEL CORP20 citations91
US5892931AApr 6, 1999
Method and apparatus for splitting a bus target response between two devices in a computer system
INTEL CORP21 citations91
US5862349AJan 19, 1999
Method and apparatus for docking and undocking a notebook computer
INTEL CORP50 citations91
US5671421ASep 23, 1997
Serial interrupt bus protocol
INTEL CORP22 citations91
US6021506AFeb 1, 2000
Method and apparatus for stopping a bus clock while there are no activities on a bus
INTEL CORP43 citations89
US5471672ANov 28, 1995
Method for implementing a high speed computer graphics bus
INTEL CORP24 citations89
US6574738B2Jun 3, 2003
Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems
INTEL CORP14 citations83
US5748918AMay 5, 1998
Method and apparatus for supporting two subtractive decode agents on the same bus in a computer system
INTEL CORP12 citations72
US5369643ANov 29, 1994
Method and apparatus for mapping test signals of an integrated circuit
INTEL CORP8 citations67