Inventor
DEMENT JONATHAN JAMES
US19 patents
⚠️ This page may combine multiple inventors who share the name “DEMENT JONATHAN JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS7159095B2Jan 2, 2007
Method of efficiently handling multiple page sizes in an effective to real address translation (ERAT) table
IBM62 citations96
US7401242B2Jul 15, 2008
Dynamic power management in a processor design
IBM22 citations92
US7350056B2Mar 25, 2008
Method and apparatus for issuing instructions from an issue queue in an information handling system
IBM32 citations92
US7055004B2May 30, 2006
Pseudo-LRU for a locking cache
IBM13 citations84
US7681056B2Mar 16, 2010
Dynamic power management in a processor design
IBM10 citations83
US7490224B2Feb 10, 2009
Time-of-life counter design for handling instruction flushes from a queue
IBM13 citations83
US7313673B2Dec 25, 2007
Fine grained multi-thread dispatch block mechanism
IBM18 citations83
US7913070B2Mar 22, 2011
Time-of-life counter for handling instruction flushes from a queue
IBM4 citations62
US7370176B2May 6, 2008
System and method for high frequency stall design
IBM2 citations62
US7328330B2Feb 5, 2008
Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor
IBM3 citations62
US6967510B2Nov 22, 2005
Time-base implementation for correcting accumulative error with chip frequency scaling
IBM2 citations62
US8028151B2Sep 27, 2011
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
IBM2 citations60
US7516275B2Apr 7, 2009
Pseudo-LRU virtual counter for a locking cache
IBM3 citations60
US7831808B2Nov 9, 2010
Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor
IBM0 citations52
US7475232B2Jan 6, 2009
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
IBM0 citations50
US7877550B2Jan 25, 2011
Bus controller initiated write-through mechanism with hardware automatically generated clean command
IBM0 citations46
US7472229B2Dec 30, 2008
Bus controller initiated write-through mechanism
IBM0 citations46
BURNS ADAM PATRICK
2 patentsUS8244979B2Aug 14, 2012
System and method for cache-locking mechanism using translation table attributes for replacement class ID determination
BURNS ADAM PATRICK8 citations76
US8099579B2Jan 17, 2012
System and method for cache-locking mechanism using segment table attributes for replacement class ID determination
BURNS ADAM PATRICK0 citations44