Inventor
HEBIG TRAVIS REYNOLD
US16 patents
⚠️ This page may combine multiple inventors who share the name “HEBIG TRAVIS REYNOLD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
12 patentsUS7684263B2Mar 23, 2010
Method and circuit for implementing enhanced SRAM write and read performance ring oscillator
IBM8 citations84
US7609542B2Oct 27, 2009
Implementing enhanced SRAM read performance sort ring oscillator (PSRO)
IBM10 citations84
US7480170B1Jan 20, 2009
Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO)
IBM9 citations84
US7924633B2Apr 12, 2011
Implementing boosted wordline voltage in memories
IBM13 citations83
US7525367B2Apr 28, 2009
Method for implementing level shifter circuits for integrated circuits
IBM12 citations83
US7505340B1Mar 17, 2009
Method for implementing SRAM cell write performance evaluation
IBM10 citations83
US7737757B2Jun 15, 2010
Low power level shifting latch circuits with gated feedback for high speed integrated circuits
IBM9 citations82
US7835176B2Nov 16, 2010
Implementing enhanced dual mode SRAM performance screen ring oscillator
IBM4 citations62
US7788554B2Aug 31, 2010
Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation
IBM3 citations62
US7768851B2Aug 3, 2010
Apparatus for implementing SRAM cell write performance evaluation
IBM1 citations62
US7911827B2Mar 22, 2011
Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels
IBM3 citations61
US7724585B2May 25, 2010
Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability
IBM4 citations61
BEHRENDS DERICK GARDNER
3 patentsUS8159260B1Apr 17, 2012
Delay chain burn-in for increased repeatability of physically unclonable functions
BEHRENDS DERICK GARDNER15 citations82
US8467230B2Jun 18, 2013
Data security for dynamic random access memory using body bias to clear data at power-up
BEHRENDS DERICK GARDNER2 citations60
US8860141B2Oct 14, 2014
Layout to minimize FET variation in small dimension photolithography
BEHRENDS DERICK GARDNER0 citations50