Inventor

GEROUSIS VASSILIOS

US19 patents

⚠️ This page may combine multiple inventors who share the name “GEROUSIS VASSILIOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GEROUSIS VASSILIOS

SAMSUNG ELECTRONICS CO LTD

Semiconductor device and method for making the same

Power distribution network using buried power rail

Semiconductor cell blocks having non-integer multiple of cell heights

Method of forming a thermal shield in a monolithic 3-d integrated circuit

Method of forming isolation dielectrics for stacked field effect transistors (FETs)

Method of forming a thermal shield in a monolithic 3-D integrated circuit

Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding

Semiconductor cell blocks having non-integer multiple of cell heights

CHANG HONGLIANG

Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits

System and method of computing pin criticalities under process variations for timing analysis and optimization

Static timing analysis with design-specific on chip variation de-rating factors

CADENCE DESIGN SYSTEMS INC

Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designs

Methods, systems, and articles of manufacture for implementing correct-by-construction physical designs with multiple-patterning-awareness

ZHANG LIZHENG

Method and system for performing statistical leakage characterization, analysis, and modeling

Method and system for performing statistical leakage characterization, analysis, and modeling

CADENCE DESIGN SYSTEM INC

Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design

LI JIANMIN

Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniques

SEZGINER ABDURRAHMAN

Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning

IBM

Orthogonal circuit element routing