Inventor
SCHOENBORN PHILIPPE
US29 patents
⚠️ This page may combine multiple inventors who share the name “SCHOENBORN PHILIPPE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
27 patentsUS5902704AMay 11, 1999
Process for forming photoresist mask over integrated circuit structures with critical dimension control
LSI LOGIC CORP219 citations98
US5474648ADec 12, 1995
Uniform and repeatable plasma processing
LSI LOGIC CORP237 citations97
US5401350AMar 28, 1995
Coil configurations for improved uniformity in inductively coupled plasma systems
LSI LOGIC CORP370 citations97
US6350700B1Feb 26, 2002
Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
LSI LOGIC CORP59 citations96
US5362356ANov 8, 1994
Plasma etching process control
LSI LOGIC CORP85 citations96
US5298110AMar 29, 1994
Trench planarization techniques
LSI LOGIC CORP48 citations96
US5290396AMar 1, 1994
Trench planarization techniques
LSI LOGIC CORP37 citations96
US5242536ASep 7, 1993
Anisotropic polysilicon etching process
LSI LOGIC CORP68 citations96
US5639519AJun 17, 1997
Method for igniting low pressure inductively coupled plasma
LSI LOGIC CORP40 citations95
US5468296ANov 21, 1995
Apparatus for igniting low pressure inductively coupled plasma
LSI LOGIC CORP80 citations95
US6673721B1Jan 6, 2004
Process for removal of photoresist mask used for making vias in low k carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask
LSI LOGIC CORP29 citations92
US6503840B2Jan 7, 2003
Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning
LSI LOGIC CORP40 citations92
US5413966AMay 9, 1995
Shallow trench etch
LSI LOGIC CORP33 citations92
US5877530AMar 2, 1999
Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation
LSI LOGIC CORP44 citations91
US5578165ANov 26, 1996
Coil configurations for improved uniformity in inductively coupled plasma systems
LSI LOGIC CORP31 citations91
US5598021AJan 28, 1997
MOS structure with hot carrier reduction
LSI LOGIC CORP43 citations90
US6713386B1Mar 30, 2004
Method of preventing resist poisoning in dual damascene structures
LSI LOGIC CORP17 citations89
US7071113B2Jul 4, 2006
Process for removal of photoresist mask used for making vias in low K carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask
LSI LOGIC CORP16 citations84
US6559048B1May 6, 2003
Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning
LSI LOGIC CORP15 citations84
US6743725B1Jun 1, 2004
High selectivity SiC etch in integrated circuit fabrication
LSI LOGIC CORP18 citations81
US6576404B2Jun 10, 2003
Carbon-doped hard mask and method of passivating structures during semiconductor device fabrication
LSI LOGIC CORP13 citations81
US5082792AJan 21, 1992
Forming a physical structure on an integrated circuit device and determining its size by measurement of resistance
LSI LOGIC CORP18 citations74
US6062163AMay 16, 2000
Plasma initiating assembly
LSI LOGIC CORP12 citations73
US6846569B2Jan 25, 2005
Carbon-doped hard mask and method of passivating structures during semiconductor device fabrication
LSI LOGIC CORP9 citations71
US6506670B2Jan 14, 2003
Self aligned gate
LSI LOGIC CORP4 citations63
US6969683B2Nov 29, 2005
Method of preventing resist poisoning in dual damascene structures
LSI LOGIC CORP3 citations60
US5663083ASep 2, 1997
Process for making improved MOS structure with hot carrier reduction
LSI LOGIC CORP1 citations49