Inventor

HUANG WEN-TUO

TW50 patents

⚠️ This page may combine multiple inventors who share the name “HUANG WEN-TUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG WEN-TUO

TAIWAN SEMICONDUCTOR MFG CO LTD

Strap-cell architecture for embedded memory

Architecture to improve cell size for compact array of split gate flash cell with buried common source structure

3DIC structure for high voltage device on a SOI substrate

Polysilicon resistor structures

Polysilicon resistor structures

Method to improve memory cell erasure

High endurance non-volatile memory cell

Control gate strap layout to improve a word line etch process window

Device-region layout for embedded flash

Control gate strap layout to improve a word line etch process window

Semiconductor device and manufacturing method thereof

Non-volatile memory semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor packages and methods of manufacturing thereof

Polysilicon resistor structures

Bonded wafer device structure and methods for making the same

ONON sidewall structure for memory device and method for making the same

High voltage transistor structures

Semiconductor feature and method for manufacturing the same

Strap-cell architecture for embedded memory

Device-region layout for embedded flash

ONON sidewall structure for memory device and method for making the same

Bonded wafer device structure and methods for making the same

High voltage transistor structure

ONON sidewall structure for memory device and methods of making the same

Semiconductor device and manufacturing method thereof

Strap-cell architecture for embedded memory

Semiconductor feature and method for manufacturing the same

Device-region layout for embedded flash

Semiconductor device and manufacturing method thereof

Bonded wafer device structure and methods for making the same

Strap-cell architecture for embedded memory

Method to reduce kink effect in semiconductor devices

Non-volatile memory semiconductor device with electrostatic discharge protection, planarization layers, and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Shared pad/bridge layout for a 3D IC

Method of forming a semiconductor device with a dual gate dielectric layer having middle portion thinner than the edge portions

Semiconductor memory device and manufacturing method thereof

Testing structure for an integrated chip having a high-voltage device

Device-region layout for embedded flash

Method to reduce kink effect in semiconductor devices

Semiconductor device and manufacturing method thereof

Backside leakage prevention

High bandwidth package structure

Semiconductor structure for memory device and method for forming the same

TAIWAN SEMICONDUCTOR MFG

Methods and apparatus for non-volatile memory cells with increased programming efficiency

Architecture to improve cell size for compact array of split gate flash cell

Methods and apparatus for non-volatile memory cells with increased programming efficiency