P

Inventor

SABHARWAL DEEPAK

US18 patents
⚠️ This page may combine multiple inventors who share the name “SABHARWAL DEEPAK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VIRAGE LOGIC CORP

13 patents
US7061794B1Jun 13, 2006

Wordline-based source-biasing scheme for reducing memory cell leakage

VIRAGE LOGIC CORP25 citations92
US6853572B1Feb 8, 2005

Methods and apparatuses for a ROM memory array having twisted source or bit lines

VIRAGE LOGIC CORP39 citations92
US6738953B1May 18, 2004

System and method for memory characterization

VIRAGE LOGIC CORP26 citations92
US7002827B1Feb 21, 2006

Methods and apparatuses for a ROM memory array having a virtually grounded line

VIRAGE LOGIC CORP45 citations90
US7692964B1Apr 6, 2010

Source-biased SRAM cell with reduced memory cell leakage

VIRAGE LOGIC CORP13 citations83
US6711092B1Mar 23, 2004

Semiconductor memory with multiple timing loops

VIRAGE LOGIC CORP15 citations83
US7298659B1Nov 20, 2007

Method and system for accelerated detection of weak bits in an SRAM memory device

VIRAGE LOGIC CORP10 citations80
US7251186B1Jul 31, 2007

Multi-port memory utilizing an array of single-port memory cells

VIRAGE LOGIC CORP15 citations80
US6587364B1Jul 1, 2003

System and method for increasing performance in a compilable read-only memory (ROM)

VIRAGE LOGIC CORP13 citations80
US6424556B1Jul 23, 2002

System and method for increasing performance in a compilable read-only memory (ROM)

VIRAGE LOGIC CORP10 citations69
US7376013B2May 20, 2008

Compact virtual ground diffusion programmable ROM array architecture, system and method

VIRAGE LOGIC CORP2 citations62
US7197438B1Mar 27, 2007

System and method for memory compiler characterization

VIRAGE LOGIC CORP4 citations60
US7609550B2Oct 27, 2009

Compact virtual ground diffusion programmable ROM array architecture, system and method

VIRAGE LOGIC CORP0 citations51

SYNOPSYS INC

4 patents

SACHAN VINEET KUMAR

1 patent