Inventor
BELL D MICHAEL
US23 patents
Patents
23 patentsUS5905876AMay 18, 1999
Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
INTEL CORP163 citations99
US6070207AMay 30, 2000
Hot plug connected I/O bus for computer system
INTEL CORP119 citations98
US5594882AJan 14, 1997
PCI split transactions utilizing dual address cycle
INTEL CORP98 citations98
US5546546AAug 13, 1996
Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
INTEL CORP181 citations98
US6021451AFeb 1, 2000
Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
INTEL CORP102 citations97
US5535340AJul 9, 1996
Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge
INTEL CORP122 citations97
US6081851AJun 27, 2000
Method and apparatus for programming a remote DMA engine residing on a first bus from a destination residing on a second bus
INTEL CORP47 citations96
US5835739ANov 10, 1998
Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
INTEL CORP49 citations96
US5434996AJul 18, 1995
Synchronous/asynchronous clock net with autosense
INTEL CORP99 citations96
US5410707AApr 25, 1995
Bootstrap loading from external memory including disabling a reset from a keyboard controller while an operating system load signal is active
INTEL CORP99 citations96
US6330630B1Dec 11, 2001
Computer system having improved data transfer across a bus bridge
INTEL CORP49 citations92
US6317799B1Nov 13, 2001
Destination controlled remote DMA engine
INTEL CORP37 citations92
US6266778B1Jul 24, 2001
Split transaction I/O bus with pre-specified timing protocols to synchronously transmit packets between devices over multiple cycles
INTEL CORP24 citations92
US6108736AAug 22, 2000
System and method of flow control for a high speed bus
INTEL CORP49 citations92
US6047120AApr 4, 2000
Dual mode bus bridge for interfacing a host bus and a personal computer interface bus
INTEL CORP26 citations92
US5828865AOct 27, 1998
Dual mode bus bridge for interfacing a host bus and a personal computer interface bus
INTEL CORP38 citations92
US6148356ANov 14, 2000
Scalable computer system
INTEL CORP43 citations89
US7480747B2Jan 20, 2009
Method and apparatus to reduce latency and improve throughput of input/output data in a processor
INTEL CORP9 citations84
US7107371B1Sep 12, 2006
Method and apparatus for providing and embedding control information in a bus system
INTEL CORP7 citations74
US6088370AJul 11, 2000
Fast 16 bit, split transaction I/O bus
INTEL CORP5 citations74
US6134622AOct 17, 2000
Dual mode bus bridge for computer system
INTEL CORP12 citations69
US7535918B2May 19, 2009
Copy on access mechanisms for low latency data movement
INTEL CORP4 citations63
US7016989B1Mar 21, 2006
Fast 16 bit, split transaction I/O bus
INTEL CORP2 citations63