Inventor

PARK HEONCHUL

US36 patents

⚠️ This page may combine multiple inventors who share the name “PARK HEONCHUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARK HEONCHUL

CEREMORPHIC INC

Synchronization of asymmetric processors executing in quasi-dual processor lock step computing systems

System for error detection and correction in a multi-thread processor

System and method for storing and accessing preprocessed data

Programmable multi-level data access address generator

Programmable multi-level data access address generator

Multiple interfaces for multiple threads of a hardware multi-thread microprocessor

Reconfigurable SIMD engine

Fast recovery for dual core lock step

Core processor and redundant branch processor with control flow attack detection

Multi-threaded secure processor with control flow attack detection

System and method for a pipelined multi-layer switching network

Multi-threaded processor with power granularity and thread granularity

Storage of delay-logic values for enhanced fault recovery for dual processor lock step computing systems

System for error detection and correction in a multi-thread processor

SAMSUNG ELECTRONICS CO LTD

Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor

Scalable width vector processor architecture for efficient emulation

Resizable and relocatable memory scratch pad as a cache slice

Single-instruction-multiple-data processing using multiple banks of vector registers

Execution unit for processing a data stream independently and in parallel

Computer methods for writing a scalar value to a vector

Load and store unit for a vector processor

Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions

Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor

Opportunistic operand forwarding to minimize register file read ports

Multifunction data aligner in wide data width processor

Instruction fetch unit including instruction buffer and secondary or branch target buffer that transfers prefetched instructions to the instruction buffer

Method for performing dead-zone quantization in a single processor instruction

REDPINE SIGNALS INC

Multiple thread in-order issue in-order completion DSP and micro-controller

Flexible multi-channel multi-thread media access controller and physical layer interface for wireless networks

Reconfigurable multi-thread processor for simultaneous operations on split instructions and operands

INFINEON TECHNOLOGIES CORP

Area efficient clock inverting circuit for design for testability

Method and apparatus for updating a program counter

SAMSUNG ELECTRONICS INC

Efficient context saving and restoring in a multi-tasking computing system environment

UNIV SO CALIFORNIA

Single chip design for fast image compression

INFINEON TECHNOLOGIES AG

Three input variable subfield comparation for fast matching

VENKATESH NARASIMHAN

Multi-thread media access controller with per-thread MAC address