Inventor

OLARIG SOMPONG P

US67 patents

⚠️ This page may combine multiple inventors who share the name “OLARIG SOMPONG P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OLARIG SOMPONG P

COMPAQ COMPUTER CORP

Fault tolerant memory

Dual purpose apparatus, method and system for accelerated graphics port and fibre channel arbitrated loop interfaces

Hardware theft-protection architecture

Secure two-piece user authentication in a computer network

Dual purpose apparatus method and system for accelerated graphics or second memory interface

Installation and removal of components of a computer

Method and apparatus for detecting insertion and removal of a memory module using standard connectors

Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses

Error checking and correcting for burst DRAM devices

System and method for performing secure device communications in a peer-to-peer bus architecture

Method for the secure remote flashing of the BIOS of a computer

Fault tolerant memory

Method and apparatus for determining a processor failure in a multiprocessor computer

Data error detection and correction

Fault-tolerant interconnection means in a computer system

Error detection and correction

error detection and correction

System and method for secure information transmission over a network

Apparatus, method and system for remote peripheral component interconnect bus using accelerated graphics port logic circuits

Computer architecture with automatic disabling of hardware/software features using satellite positioning data

Method and apparatus for multicasting on a bus

Programmable memory device that supports multiple operational modes

Hot processor swap in a multiprocessor personal computer system

HEWLETT PACKARD DEVELOPMENT CO

Data redundancy in a hot pluggable, large symmetric multi-processor system

Method and apparatus for scheduling memory calibrations based on transactions

Technique for implementing chipkill in a memory system

Location-based security for a portable computer

Installation and removal of components of a computer

Fault-tolerant switch architecture

Dynamic cache partitioning

Raid memory

CPU power sequence for large multiprocessor systems

Disk storage with transparent overflow to network storage

System and method for allocating fail-over memory

Fail-over of multiple memory blocks in multiple memory modules in computer system

Multi-mode graphics address remapping table for an accelerated graphics port device

Dynamic cache partitioning

Method and apparatus for restoring computer resources

Main memory controller adapted to correct corrupted data by xoring corrupted data to directly generate correct data

Method and apparatus for locking/unlocking via platform management bus

COMPAQ INFORMATION TECHNOLOGIE

Fail-over of multiple memory blocks in multiple memory modules in computer system

Computer system with adaptive heartbeat

Adaptive calibration technique for high speed memory devices

“J” system for securing a portable computer which optionally requires an entry of an invalid power on password (POP), by forcing an entry of a valid POP

Apparatus, method and system for using cache memory as fail-over memory

Command and control infrastructure for a computer system using the computer&#39;s power rail

Method and apparatus for providing interchassis communication and management

HEWLETT PACKARD CO

Memory controller with temperature sensors

COMPACT COMPUTER CORP

Method for the secure remote flashing of a BIOS memory

COMPAQ COMPUTER CORP INC

Method and apparatus for performing error detection and correction with memory devices

Command and control infrastructure for a computer system using the computer's power rail