Inventor

KADOSH DANIEL

US114 patents

Patents

50 patents

US6080640AJun 27, 2000

Metal attachment method and structure for attaching substrates at low temperatures

ADVANCED MICRO DEVICES INC291 citations99

US6075268AJun 13, 2000

Ultra high density inverter using a stacked transistor arrangement

ADVANCED MICRO DEVICES INC256 citations99

US5770483AJun 23, 1998

Multi-level transistor fabrication method with high performance drain-to-gate connection

ADVANCED MICRO DEVICES INC256 citations99

US6097096AAug 1, 2000

Metal attachment method and structure for attaching substrates at low temperatures

ADVANCED MICRO DEVICES INC116 citations98

US5885877AMar 23, 1999

Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

ADVANCED MICRO DEVICES INC107 citations98

US7198964B1Apr 3, 2007

Method and apparatus for detecting faults using principal component analysis parameter groupings

ADVANCED MICRO DEVICES INC64 citations97

US5981354ANov 9, 1999

Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process

ADVANCED MICRO DEVICES INC110 citations97

US6506642B1Jan 14, 2003

Removable spacer technique

ADVANCED MICRO DEVICES INC74 citations96

US6355955B1Mar 12, 2002

Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation

ADVANCED MICRO DEVICES INC64 citations96

US6225151B1May 1, 2001

Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion

ADVANCED MICRO DEVICES INC68 citations96

US6172381B1Jan 9, 2001

Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall

ADVANCED MICRO DEVICES INC61 citations96

US6069398AMay 30, 2000

Thin film resistor and fabrication method thereof

ADVANCED MICRO DEVICES INC67 citations96

US6037629AMar 14, 2000

Trench transistor and isolation trench

ADVANCED MICRO DEVICES INC53 citations96

US5949092ASep 7, 1999

Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator

ADVANCED MICRO DEVICES INC62 citations96

US5937301AAug 10, 1999

Method of making a semiconductor device having sidewall spacers with improved profiles

ADVANCED MICRO DEVICES INC55 citations96

US5933721AAug 3, 1999

Method for fabricating differential threshold voltage transistor pair

ADVANCED MICRO DEVICES INC64 citations96

US5869379AFeb 9, 1999

Method of forming air gap spacer for high performance MOSFETS'

ADVANCED MICRO DEVICES INC73 citations96

US5866934AFeb 2, 1999

Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure

ADVANCED MICRO DEVICES INC45 citations96

US5852310ADec 22, 1998

Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto

ADVANCED MICRO DEVICES INC48 citations96

US5714394AFeb 3, 1998

Method of making an ultra high density NAND gate using a stacked transistor arrangement

ADVANCED MICRO DEVICES INC64 citations96

US5677224AOct 14, 1997

Method of making asymmetrical N-channel and P-channel devices

ADVANCED MICRO DEVICES INC52 citations96

US6764908B1Jul 20, 2004

Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents

ADVANCED MICRO DEVICES INC50 citations93

US6589847B1Jul 8, 2003

Tilted counter-doped implant to sharpen halo profile

ADVANCED MICRO DEVICES INC47 citations93

US6504218B1Jan 7, 2003

Asymmetrical N-channel and P-channel devices

ADVANCED MICRO DEVICES INC16 citations93

US6383872B1May 7, 2002

Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure

ADVANCED MICRO DEVICES INC16 citations93

US6358828B1Mar 19, 2002

Ultra high density series-connected transistors formed on separate elevational levels

ADVANCED MICRO DEVICES INC38 citations93

US6261885B1Jul 17, 2001

Method for forming integrated circuit gate conductors from dual layers of polysilicon

ADVANCED MICRO DEVICES INC18 citations93

US6259118B1Jul 10, 2001

Ultra high density NOR gate using a stacked transistor arrangement

ADVANCED MICRO DEVICES INC36 citations93

US6232637B1May 15, 2001

Semiconductor fabrication having multi-level transistors and high density interconnect therebetween

ADVANCED MICRO DEVICES INC30 citations93

US6218251B1Apr 17, 2001

Asymmetrical IGFET devices with spacers formed by HDP techniques

ADVANCED MICRO DEVICES INC29 citations93

US6172402B1Jan 9, 2001

Integrated circuit having transistors that include insulative punchthrough regions and method of formation

ADVANCED MICRO DEVICES INC20 citations93

US6121643ASep 19, 2000

Semiconductor device having a group of high performance transistors and method of manufacture thereof

ADVANCED MICRO DEVICES INC19 citations93

US6096591AAug 1, 2000

Method of making an IGFET and a protected resistor with reduced processing steps

ADVANCED MICRO DEVICES INC36 citations93

US6078080AJun 20, 2000

Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region

ADVANCED MICRO DEVICES INC37 citations93

US6027964AFeb 22, 2000

Method of making an IGFET with a selectively doped gate in combination with a protected resistor

ADVANCED MICRO DEVICES INC24 citations93

US6027978AFeb 22, 2000

Method of making an IGFET with a non-uniform lateral doping profile in the channel region

ADVANCED MICRO DEVICES INC40 citations93

US6004849ADec 21, 1999

Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source

ADVANCED MICRO DEVICES INC28 citations93

US6005272ADec 21, 1999

Trench transistor with source contact in trench

ADVANCED MICRO DEVICES INC26 citations93

US5994779ANov 30, 1999

Semiconductor fabrication employing a spacer metallization technique

ADVANCED MICRO DEVICES INC19 citations93

US5985724ANov 16, 1999

Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer

ADVANCED MICRO DEVICES INC34 citations93

US5926700AJul 20, 1999

Semiconductor fabrication having multi-level transistors and high density interconnect therebetween

ADVANCED MICRO DEVICES INC20 citations93

US5923982AJul 13, 1999

Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps

ADVANCED MICRO DEVICES INC32 citations93

US5912188AJun 15, 1999

Method of forming a contact hole in an interlevel dielectric layer using dual etch stops

ADVANCED MICRO DEVICES INC49 citations93

US5909622AJun 1, 1999

Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant

ADVANCED MICRO DEVICES INC31 citations93

US5904529AMay 18, 1999

Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate

ADVANCED MICRO DEVICES INC29 citations93

US5898189AApr 27, 1999

Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method

ADVANCED MICRO DEVICES INC22 citations93

US5893739AApr 13, 1999

Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer

ADVANCED MICRO DEVICES INC20 citations93

US5888853AMar 30, 1999

Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof

ADVANCED MICRO DEVICES INC35 citations93

US5888872AMar 30, 1999

Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall

ADVANCED MICRO DEVICES INC28 citations93

US5874341AFeb 23, 1999

Method of forming trench transistor with source contact in trench

ADVANCED MICRO DEVICES INC40 citations93

Showing the top 50 of 114 patents by PatentIndex Score.

KADOSH DANIEL

Patents

Metal attachment method and structure for attaching substrates at low temperatures

Ultra high density inverter using a stacked transistor arrangement

Multi-level transistor fabrication method with high performance drain-to-gate connection

Metal attachment method and structure for attaching substrates at low temperatures

Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

Method and apparatus for detecting faults using principal component analysis parameter groupings

Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process

Removable spacer technique

Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation

Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion

Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall

Thin film resistor and fabrication method thereof

Trench transistor and isolation trench

Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator

Method of making a semiconductor device having sidewall spacers with improved profiles

Method for fabricating differential threshold voltage transistor pair

Method of forming air gap spacer for high performance MOSFETS&#39;

Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure

Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto

Method of making an ultra high density NAND gate using a stacked transistor arrangement

Method of making asymmetrical N-channel and P-channel devices

Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents

Tilted counter-doped implant to sharpen halo profile

Asymmetrical N-channel and P-channel devices

Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure

Ultra high density series-connected transistors formed on separate elevational levels

Method for forming integrated circuit gate conductors from dual layers of polysilicon

Ultra high density NOR gate using a stacked transistor arrangement

Semiconductor fabrication having multi-level transistors and high density interconnect therebetween

Asymmetrical IGFET devices with spacers formed by HDP techniques

Integrated circuit having transistors that include insulative punchthrough regions and method of formation

Semiconductor device having a group of high performance transistors and method of manufacture thereof

Method of making an IGFET and a protected resistor with reduced processing steps

Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region

Method of making an IGFET with a selectively doped gate in combination with a protected resistor

Method of making an IGFET with a non-uniform lateral doping profile in the channel region

Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source

Trench transistor with source contact in trench

Semiconductor fabrication employing a spacer metallization technique

Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer

Semiconductor fabrication having multi-level transistors and high density interconnect therebetween

Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps

Method of forming a contact hole in an interlevel dielectric layer using dual etch stops

Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant

Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate

Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method

Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer

Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof

Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall

Method of forming trench transistor with source contact in trench

Method of forming air gap spacer for high performance MOSFETS'