Inventor

HAUSE FREDERICK N

US110 patents

Patents

50 patents

US6274894B1Aug 14, 2001

Trench transistor with localized source/drain regions implanted through selectively grown oxide layer

ADVANCED MICRO DEVICES INC113 citations98

US5885877AMar 23, 1999

Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

ADVANCED MICRO DEVICES INC107 citations98

US6410967B1Jun 25, 2002

Transistor having enhanced metal silicide and a self-aligned gate electrode

ADVANCED MICRO DEVICES INC76 citations96

US6268637B1Jul 31, 2001

Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication

ADVANCED MICRO DEVICES INC73 citations96

US6259142B1Jul 10, 2001

Multiple split gate semiconductor device and fabrication method

ADVANCED MICRO DEVICES INC67 citations96

US6255703B1Jul 3, 2001

Device with lower LDD resistance

ADVANCED MICRO DEVICES INC69 citations96

US6225151B1May 1, 2001

Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion

ADVANCED MICRO DEVICES INC68 citations96

US6201278B1Mar 13, 2001

Trench transistor with insulative spacers

ADVANCED MICRO DEVICES INC48 citations96

US6084280AJul 4, 2000

Transistor having a metal silicide self-aligned to the gate

ADVANCED MICRO DEVICES INC82 citations96

US6069398AMay 30, 2000

Thin film resistor and fabrication method thereof

ADVANCED MICRO DEVICES INC67 citations96

US5933721AAug 3, 1999

Method for fabricating differential threshold voltage transistor pair

ADVANCED MICRO DEVICES INC64 citations96

US5933717AAug 3, 1999

Vertical transistor interconnect structure and fabrication method thereof

ADVANCED MICRO DEVICES INC60 citations96

US5930634AJul 27, 1999

Method of making an IGFET with a multilevel gate

ADVANCED MICRO DEVICES INC63 citations96

US5899732AMay 4, 1999

Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device

ADVANCED MICRO DEVICES INC83 citations96

US5888675AMar 30, 1999

Reticle that compensates for radiation-induced lens error in a photolithographic system

ADVANCED MICRO DEVICES INC68 citations96

US5840451ANov 24, 1998

Individually controllable radiation sources for providing an image pattern in a photolithographic system

ADVANCED MICRO DEVICES INC61 citations96

US5710054AJan 20, 1998

Method of forming a shallow junction by diffusion from a silicon-based spacer

ADVANCED MICRO DEVICES INC92 citations96

US6226781B1May 1, 2001

Modifying a design layer of an integrated circuit using overlying and underlying design layers

ADVANCED MICRO DEVICES INC73 citations94

US6661057B1Dec 9, 2003

Tri-level segmented control transistor and fabrication method

ADVANCED MICRO DEVICES INC29 citations93

US6552776B1Apr 22, 2003

Photolithographic system including light filter that compensates for lens error

ADVANCED MICRO DEVICES INC20 citations93

US6380055B2Apr 30, 2002

Dopant diffusion-retarding barrier region formed within polysilicon gate layer

ADVANCED MICRO DEVICES INC36 citations93

US6352885B1Mar 5, 2002

Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same

ADVANCED MICRO DEVICES INC46 citations93

US6261908B1Jul 17, 2001

Buried local interconnect

ADVANCED MICRO DEVICES INC34 citations93

US6252283B1Jun 26, 2001

CMOS transistor design for shared N+/P+ electrode with enhanced device performance

ADVANCED MICRO DEVICES INC40 citations93

US6242776B1Jun 5, 2001

Device improvement by lowering LDD resistance with new silicide process

ADVANCED MICRO DEVICES INC41 citations93

US6218250B1Apr 17, 2001

Method and apparatus for minimizing parasitic resistance of semiconductor devices

ADVANCED MICRO DEVICES INC19 citations93

US6197645B1Mar 6, 2001

Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls

ADVANCED MICRO DEVICES INC44 citations93

US6194768B1Feb 27, 2001

High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure

ADVANCED MICRO DEVICES INC21 citations93

US6188114B1Feb 13, 2001

Method of forming an insulated-gate field-effect transistor with metal spacers

ADVANCED MICRO DEVICES INC19 citations93

US6166354ADec 26, 2000

System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication

ADVANCED MICRO DEVICES INC37 citations93

US6146978ANov 14, 2000

Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance

ADVANCED MICRO DEVICES INC23 citations93

US6140167AOct 31, 2000

High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation

ADVANCED MICRO DEVICES INC35 citations93

US6140674AOct 31, 2000

Buried trench capacitor

ADVANCED MICRO DEVICES INC42 citations93

US6140677AOct 31, 2000

Semiconductor topography for a high speed MOSFET having an ultra narrow gate

ADVANCED MICRO DEVICES INC23 citations93

US6133124AOct 17, 2000

Device improvement by source to drain resistance lowering through undersilicidation

ADVANCED MICRO DEVICES INC38 citations93

US6100146AAug 8, 2000

Method of forming trench transistor with insulative spacers

ADVANCED MICRO DEVICES INC18 citations93

US6087706AJul 11, 2000

Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls

ADVANCED MICRO DEVICES INC51 citations93

US6080629AJun 27, 2000

Ion implantation into a gate electrode layer using an implant profile displacement layer

ADVANCED MICRO DEVICES INC51 citations93

US6048785AApr 11, 2000

Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching

ADVANCED MICRO DEVICES INC19 citations93

US6030752AFeb 29, 2000

Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device

ADVANCED MICRO DEVICES INC20 citations93

US6005272ADec 21, 1999

Trench transistor with source contact in trench

ADVANCED MICRO DEVICES INC26 citations93

US5976956ANov 2, 1999

Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device

ADVANCED MICRO DEVICES INC40 citations93

US5962894AOct 5, 1999

Trench transistor with metal spacers

ADVANCED MICRO DEVICES INC24 citations93

US5937299AAug 10, 1999

Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls

ADVANCED MICRO DEVICES INC44 citations93

US5923980AJul 13, 1999

Trench transistor with localized source/drain regions implanted through voids in trench

ADVANCED MICRO DEVICES INC24 citations93

Showing the top 50 of 110 patents by PatentIndex Score.

HAUSE FREDERICK N

Patents

Low-bandgap source and drain formation for short-channel MOS transistors

Method and apparatus for in situ anneal during ion implant

Method of making NMOS and PMOS devices with reduced masking steps

Transistor with buried insulative layer beneath the channel region

Method of channel doping using diffusion from implanted polysilicon

Trench transistor with localized source/drain regions implanted through selectively grown oxide layer

Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

Transistor having enhanced metal silicide and a self-aligned gate electrode

Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication

Multiple split gate semiconductor device and fabrication method

Device with lower LDD resistance

Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion

Trench transistor with insulative spacers

Transistor having a metal silicide self-aligned to the gate

Thin film resistor and fabrication method thereof

Method for fabricating differential threshold voltage transistor pair

Vertical transistor interconnect structure and fabrication method thereof

Method of making an IGFET with a multilevel gate

Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device

Reticle that compensates for radiation-induced lens error in a photolithographic system

Individually controllable radiation sources for providing an image pattern in a photolithographic system

Method of forming a shallow junction by diffusion from a silicon-based spacer

Modifying a design layer of an integrated circuit using overlying and underlying design layers

Tri-level segmented control transistor and fabrication method

Photolithographic system including light filter that compensates for lens error

Dopant diffusion-retarding barrier region formed within polysilicon gate layer

Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same

Buried local interconnect

CMOS transistor design for shared N+/P+ electrode with enhanced device performance

Device improvement by lowering LDD resistance with new silicide process

Method and apparatus for minimizing parasitic resistance of semiconductor devices

Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls

High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure

Method of forming an insulated-gate field-effect transistor with metal spacers

System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication

Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance

High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation

Buried trench capacitor

Semiconductor topography for a high speed MOSFET having an ultra narrow gate

Device improvement by source to drain resistance lowering through undersilicidation

Method of forming trench transistor with insulative spacers

Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls

Ion implantation into a gate electrode layer using an implant profile displacement layer

Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching

Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device

Trench transistor with source contact in trench

Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device

Trench transistor with metal spacers

Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls

Trench transistor with localized source/drain regions implanted through voids in trench