Inventor

STEFFAN PAUL J

US69 patents

⚠️ This page may combine multiple inventors who share the name “STEFFAN PAUL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEFFAN PAUL J

ADVANCED MICRO DEVICES INC

Automatic recipe adjust and download based on process control window

Dynamic process window control using simulated wet data from current and previous layer data

Semiconductor with increased gate coupling coefficient

Electroless plated semiconductor vias and channels

Method of defining copper seed layer for selective electroless plating processing

Simplified graded LDD transistor using controlled polysilicon gate profile

Method of making a density multiplier for semiconductor device manufacturing

Universal alignment marks for semiconductor defect capture and analysis

Intelligent usage of first pass defect data for improved statistical accuracy of wafer level classification

Automatic defect classification (ADC) reclassification engine

Dual damascene process using high selectivity boundary layers

Recipe management database system

Computer generated recipe selector utilizing defect file information

Automatic defect classification system based variable sampling plan

Automatic defect classification comparator die selection system

In line yield prediction using ADC determined kill ratios die health statistics and die stacking

Global cluster pre-classification methodology

Self-aligned extension junction for reduced gate channel

Method for isolation of optical defect images

Simplified inter database communication system

Scan tool recipe server

Simplified process for fabricating flash eeprom cells

Controlled gate length and gate profile semiconductor device and manufacturing method therefor

Controlled gate length and gate profile semiconductor device

Method for fabricating graded LDD transistor using controlled polysilicon gate profile

Method for forming graded LDD transistor using controlled polysilicon gate profile

Method to accurately determine classification codes for defects during semiconductor manufacturing

Disposition tool for factory process control

Method to manufacture multiple damascene by utilizing etch selectivity

Method to manufacture dual damascene structures by utilizing short resist spacers

Multiple chip hybrid package using bump technology

Automatic defect reclassification of known propagator defects

LDD transistor using novel gate trim technique

Method to manufacture dual damascene using a phantom implant mask

Multi-chip packaging using bump technology

Automatic defect classification individual defect predicate value retention

Device level identification methodology

Composition based association engine for image archival systems

Location dependent automatic defect classification

High density contacts having rectangular cross-section for dual damascene applications

Intra-tool defect offset system

Semiconductor wafer optical scanning system and method using swath-area defect limitation

Method of forming low resistance reduced channel length transistors

Overlay radius offset shift engine

ADC based in-situ destructive analysis selection and methodology therefor

Simplified graded LDD transistor using controlled polysilicon gate profile

Automatic method to eliminate first-wafer effect

Critical area cost disposition feedback system

Method of monitoring via and trench profiles during manufacture

(unassigned)

Vehicle communication device