Inventor

YU ALLEN S

US55 patents

⚠️ This page may combine multiple inventors who share the name “YU ALLEN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU ALLEN S

ADVANCED MICRO DEVICES INC

Pitch reduction using a set of offset masks

Fabrication of dual work-function metal gate structure for complementary field effect transistors

Semiconductor with increased gate coupling coefficient

Formation of non-volatile memory device comprised of an array of vertical field effect transistor structures

Electroless plated semiconductor vias and channels

Method of defining copper seed layer for selective electroless plating processing

Simplified graded LDD transistor using controlled polysilicon gate profile

Method of making a density multiplier for semiconductor device manufacturing

Universal alignment marks for semiconductor defect capture and analysis

Dual damascene process using high selectivity boundary layers

Recipe management database system

Computer generated recipe selector utilizing defect file information

Automatic defect classification system based variable sampling plan

Automatic defect classification comparator die selection system

Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor

In line yield prediction using ADC determined kill ratios die health statistics and die stacking

Global cluster pre-classification methodology

Self-aligned extension junction for reduced gate channel

Method for isolation of optical defect images

Simplified inter database communication system

Scan tool recipe server

Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate

Controlled gate length and gate profile semiconductor device and manufacturing method therefor

Controlled gate length and gate profile semiconductor device

Method for fabricating graded LDD transistor using controlled polysilicon gate profile

Method for forming graded LDD transistor using controlled polysilicon gate profile

Method to manufacture multiple damascene by utilizing etch selectivity

Method to manufacture dual damascene structures by utilizing short resist spacers

Multiple chip hybrid package using bump technology

LDD transistor using novel gate trim technique

Method to manufacture dual damascene using a phantom implant mask

Multi-chip packaging using bump technology

Method of making vertical field effect transistor having channel length determined by the thickness of a layer of dummy material

Composition based association engine for image archival systems

Location dependent automatic defect classification

High density contacts having rectangular cross-section for dual damascene applications

Intra-tool defect offset system

Method of forming low resistance reduced channel length transistors

Overlay radius offset shift engine

ADC based in-situ destructive analysis selection and methodology therefor

Simplified graded LDD transistor using controlled polysilicon gate profile

Automatic method to eliminate first-wafer effect

Method to selectively electroplate conductive material into trenches

Automatic defect resizing tool

Reduction of via etch charging damage through the use of a conducting hard mask

Process control using ideal die data in an optical comparator scanning system

Efficient tool utilization using previous scan data

Post-via tin removal for via resistance improvement

Use of photoresist focus exposure matrix array as via etch monitor

YU ALLEN S

Fabrication of dual work-function metal gate structure for complementary field effect transistors