Inventor

LUKANC TODD

US28 patents

⚠️ This page may combine multiple inventors who share the name “LUKANC TODD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUKANC TODD

ADVANCED MICRO DEVICES INC

Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers

Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials

Method of forming a dual damascene trench and borderless via structure

Barrier layer integrity test

Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers

Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer

Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers

Nitride disposable spacer to reduce mask count in CMOS transistor formation

MOS transistor formation

Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer

Nitride disposable spacer to reduce mask count in CMOS transistor formation

Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and metal silicides

Electrical alignment test structure using local interconnect ladder resistor

Variable design rule tool

Method of strengthening photoresist to prevent pattern collapse

Phase shift mask and system and method for making the same

Use of an existing product map as a background for making test masks

Polishing pad and method for polishing porous materials

Etch bias distribution across semiconductor wafer

Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and silicides

Aluminum disposable spacer to reduce mask count in CMOS transistor formation

Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process

Aluminum disposable spacer to reduce mask count in CMOS transistor formation

Method for increasing manufacturability of a circuit layout

(unassigned)

Etch bias distribution across semiconductor wafer

GLOBALFOUNDRIES INC

Methods for optical proximity correction in the design and fabrication of integrated circuits

SPANSION LLC

Method of forming an electronic device including forming features within a mask and a selective removal process

LO WAI

Method and system for automated generation of masks for spacer formation from a desired final wafer pattern