Inventor

MAULE WARREN EDWARD

US37 patents

⚠️ This page may combine multiple inventors who share the name “MAULE WARREN EDWARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAULE WARREN EDWARD

IBM

Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices

Dynamic power management via DIMM read operation limiter

Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices

Method and system for supplier-based memory speculation in a memory subsystem of a data processing system

Power management via DIMM read operation limiter

Memory queue with supplemental locations for consecutive addresses

Data processing system and method for efficient storage of metadata in a system memory

Power management via DIMM read operation limiter

Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system

Handling interrupts by returning and requeuing currently executing interrupts for later resubmission when the currently executing interrupts are of lower priority than newly generated pending interrupts

Method for isolating faults on a clocked synchronous bus

Information handling system including doze mode control

Information handling system including non-disruptive command and data movement between storage and one or more auxiliary processors

Computer system memory controller and method of burst data ordering translation

Method and apparatus for data ordering of I/O transfers in Bi-modal Endian PowerPC systems

System for transferring data from a source device to a target device in which the address of data movement engine is determined

Clustered, buffered simms and assemblies thereof

Using bit errors from memory to alter memory command stream

Double DRAM bit steering for multiple error corrections

Double DRAM bit steering for multiple error corrections

Efficient storage of metadata in a system memory

Sequencing data on a shared data bus via a memory buffer to prevent data overlap during multiple memory read operations

Error recovery mechanism for a high-performance interconnect

Method and apparatus for reducing system snoop latency

Information handling system for modifying coherency response set to allow intervention of a read command so that the intervention is not allowed by the system memory

Process and apparatus for address extension

Information handling system including a data bus management unit, an address management unit for isolating processor buses from I/O and memory

Bidirectional off-chip driver with receiver bypass

Dram with memory independent burst lengths for reads versus writes

Information handling system including efficient power on initialization

Method and apparatus of resolving conflicting register access requests from a service processor and system processor

Executing background writes to idle DIMMS

Programmable bank/timer address folding in memory devices

Executing background writes to idle DIMMs

MAULE WARREN EDWARD

Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device

ARIMILLI RAVI KUMAR

Method and system for thread-based memory speculation in a memory subsystem of a data processing system

COTEUS PAUL W

System for error control coding for memories of different types and associated methods