Inventor
KOTTAPALLI SAILESH
US33 patents
⚠️ This page may combine multiple inventors who share the name “KOTTAPALLI SAILESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
23 patentsUS6898694B2May 24, 2005
High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle
INTEL CORP59 citations96
US6304960B1Oct 16, 2001
Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions
INTEL CORP70 citations96
US9858167B2Jan 2, 2018
Monitoring the operation of a processor
INTEL CORP16 citations92
US7984248B2Jul 19, 2011
Transaction based shared data operations in a multiprocessor environment
INTEL CORP27 citations92
US7062933B2Jun 20, 2006
Separate thermal and electrical throttling limits in processors
INTEL CORP37 citations92
US7996644B2Aug 9, 2011
Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache
INTEL CORP9 citations84
US7669009B2Feb 23, 2010
Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches
INTEL CORP11 citations84
US7149880B2Dec 12, 2006
Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor
INTEL CORP19 citations84
US7500240B2Mar 3, 2009
Apparatus and method for scheduling threads in multi-threading processors
INTEL CORP13 citations81
US7496732B2Feb 24, 2009
Method and apparatus for results speculation under run-ahead execution
INTEL CORP9 citations77
US7937709B2May 3, 2011
Synchronizing multiple threads efficiently
INTEL CORP6 citations74
US9423959B2Aug 23, 2016
Method and apparatus for store durability and ordering in a persistent memory architecture
INTEL CORP3 citations73
US9405595B2Aug 2, 2016
Synchronizing multiple threads efficiently
INTEL CORP1 citations63
US11048588B2Jun 29, 2021
Monitoring the operation of a processor
INTEL CORP0 citations62
US7401211B2Jul 15, 2008
Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor
INTEL CORP6 citations61
US7181590B2Feb 20, 2007
Method for page sharing in a processor with multiple threads and pre-validated caches
INTEL CORP6 citations59
US7149881B2Dec 12, 2006
Method and apparatus for improving dispersal performance in a processor through the use of no-op ports
INTEL CORP3 citations58
US10599547B2Mar 24, 2020
Monitoring the operation of a processor
INTEL CORP0 citations52
US8819684B2Aug 26, 2014
Synchronizing multiple threads efficiently
INTEL CORP0 citations52
US9298629B2Mar 29, 2016
Extending a cache coherency snoop broadcast protocol with directory information
INTEL CORP0 citations50
US8918592B2Dec 23, 2014
Extending a cache coherency snoop broadcast protocol with directory information
INTEL CORP0 citations50
US6721873B2Apr 13, 2004
Method and apparatus for improving dispersal performance in a processor through the use of no-op ports
INTEL CORP1 citations48
US9436605B2Sep 6, 2016
Cache coherency apparatus and method minimizing memory writeback operations
INTEL CORP0 citations41
KOTTAPALLI SAILESH
4 patentsUS8473963B2Jun 25, 2013
Synchronizing multiple threads efficiently
KOTTAPALLI SAILESH7 citations83
US8656115B2Feb 18, 2014
Extending a cache coherency snoop broadcast protocol with directory information
KOTTAPALLI SAILESH6 citations81
US8458412B2Jun 4, 2013
Transaction based shared data operations in a multiprocessor environment
KOTTAPALLI SAILESH2 citations61
US8176266B2May 8, 2012
Transaction based shared data operations in a multiprocessor environment
KOTTAPALLI SAILESH3 citations61