Inventor
DESHPANDE SANJAY R
US13 patents
⚠️ This page may combine multiple inventors who share the name “DESHPANDE SANJAY R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FREESCALE SEMICONDUCTOR INC
9 patentsUS10114748B2Oct 30, 2018
Distributed reservation based coherency protocol
FREESCALE SEMICONDUCTOR INC4 citations71
US10628329B2Apr 21, 2020
Data processing system having a coherency interconnect
FREESCALE SEMICONDUCTOR INC1 citations60
US7941499B2May 10, 2011
Interprocessor message transmission via coherency-based interconnect
FREESCALE SEMICONDUCTOR INC6 citations58
US9977750B2May 22, 2018
Coherent memory interleaving with uniform latency
FREESCALE SEMICONDUCTOR INC0 citations51
US7502893B2Mar 10, 2009
System and method for reporting cache coherency state retained within a cache hierarchy of a processing node
FREESCALE SEMICONDUCTOR INC1 citations50
US9720847B2Aug 1, 2017
Least recently used (LRU) cache replacement implementation using a FIFO storing indications of whether a way of the cache was most recently accessed
FREESCALE SEMICONDUCTOR INC1 citations49
US10346089B2Jul 9, 2019
Data processing system having a write request network and a write data network
FREESCALE SEMICONDUCTOR INC0 citations41
US9632933B2Apr 25, 2017
Efficient coherency response mechanism
FREESCALE SEMICONDUCTOR INC0 citations39
US9497141B2Nov 15, 2016
Switch point having look-ahead bypass
FREESCALE SEMICONDUCTOR INC0 citations38
DESHPANDE SANJAY R
3 patentsUS9026742B2May 5, 2015
System and method for processing potentially self-inconsistent memory transactions
DESHPANDE SANJAY R3 citations59
US9448741B2Sep 20, 2016
Piggy-back snoops for non-coherent memory transactions within distributed processing systems
DESHPANDE SANJAY R2 citations57
US9665518B2May 30, 2017
Methods and systems for controlling ordered write transactions to multiple devices using switch point networks
DESHPANDE SANJAY R0 citations36